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Simulation of a High Performance 35 nm Gate Length CMOS

Simulation of a High Performance 35 nm Gate Length CMOS. John Rozen EECE 307. Outline. Structure and Doping Profiles Scaling Effects Single Transitors Characteristics Considerations for the CMOS Conclusions. Outline. Structure and Doping Profiles Scaling Effects

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Simulation of a High Performance 35 nm Gate Length CMOS

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  1. Simulation of a High Performance 35 nm Gate Length CMOS John Rozen EECE 307

  2. Outline • Structure and Doping Profiles • Scaling Effects • Single Transitors Characteristics • Considerations for the CMOS • Conclusions

  3. Outline • Structure and Doping Profiles • Scaling Effects • Single Transitors Characteristics • Considerations for the CMOS • Conclusions

  4. Structure and Doping Profiles • Sizes: Gate length = 35nm Oxide thickness = 1.2nm • Peak concentrations: Extensions = 1 e20 cm-3 In the body = 8 e18 cm-3

  5. Outline • Structure and Doping Profiles • Scaling Effects • Single Transitors Characteristics • Considerations for the CMOS • Conclusions

  6. Scaling Effects Subsurface punchthrough Depletion regions overlap Channel length modulation Pinch-off affects saturation Vt roll-off Threshold reduced by S/D

  7. Outline • Structure and Doping Profiles • Scaling Effects • Single Transitors Characteristics • Considerations for the CMOS • Conclusions

  8. The nFET Φgate = 4.05 V (n+ poly) Fermi Statistic Lombardi Model

  9. The nFET Φgate = 4.05 V (n+ poly) Fermi Statistic Lombardi Model

  10. The nFET Gate characteristics ►Subsurface → Bad gate control Slope>200mV/dec → High leakage Ioff > 100μA/μm ►Halo required Vt roll-off Vd = 0.85V Vt ≈ 0.17V Slope≈100mV/dec Ioff ≈ 10 μA/μm Vg=0.85V Vg=0.65V Vg=0.45V

  11. The pFET Vd = -0.85V Vt ≈ -0.3V Slope≈100mV/dec Ioff ≈ 10 μA/μm Vg=-0.85V Vg=-0.65V Vg=-0.45V Φgate = 4.05 V (n+ poly) Fermi Statistic Lombardi Model

  12. Outline • Structure and Doping Profiles • Scaling Effects • Single Transitors Characteristics • Considerations for the CMOS • Conclusions

  13. Considerations for the CMOS Common background doping required

  14. Outline • Structure and Doping Profiles • Scaling Effects • Single Transitors Characteristics • Considerations for the CMOS • Conclusions

  15. Conclusions • Halo doping required to reduce SCE • Good threshold voltage and sub-threshold slope • Vt roll-off is still a concern • The off currents are quite high • Other doping profiles and other characteristics expected for the CMOS

  16. References

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