CMOS Transmission Gate

2. CMOS Transmission Gate C=VDD, B=A. C=GND, B is isolated from A. Transistors: 4=2 (transmission gate)+2 (inverter)

3. Example 1.1 GND VDD F=A

4. Example 1.2 VDD GND F=B

5. MUX

6. Transistor Count Comparison 4 inverters=8 transistors Total transistor count: 16 2 inverters=4 transistors Total transistor count: 8

7. 4-1 MUX Select either A or B 2-1 Mux Qs per MUX: 8 Qs per inverter: 2 Inverters: 2 Tota Q: 8x3+2x2=28 Select either C or D

8. 4-1 MUX Qs per TG: 4 Qs per Invter: 2 Inverters: 4 Tota Qs: 4x4+2x4=24

9. Example 2.1 VDD GND VDD GND GND GND GND VDD VDD GND

10. Example 2.2 VDD GND GND VDD VDD GND VDD VDD VDD GND

11. XOR

12. Comparison 2 inverters=4 transistors Total transistor count: 8 4 inverters=8 transistors Total transistor count: 16

13. Example 3.1 VDD GND VDD GND GND GND GND VDD VDD GND

14. Example 3.2 VDD GND GND VDD VDD VDD GND VDD VDD VDD GND

15. XNOR

16. Improper Conditions Violation: Logic at the output? Violation: Only 1 path at a time Problem: A=0; B=1. Charge Sharing

17. OR F

18. AND

19. Steps for Implementing a Logic Expression Expression: OUT=A+BC • Select control signal to create a truth table (A, B)

20. Steps for Implementing a Logic Expression 2. Create a Mux-Style Design for each row

21. Steps for Implementing a Logic Expression 3. Simplify

22. TG with Standard Gate Combination If B=1, TG is off. F is equal to

23. D GND OFF S If B=0, TG is ON. F=A Left: A=VDD, F=VDD VDD OFF VDD So, in summary, If B=0, F=A GND OFF GND If B=0, TG is ON. F=A Left: A=GND, F=GND GND S OFF D VDD

24. XOR using Standard Cell and TG If B=1, TG is off. F is equal to If B=0, F=A So F=BA’+B’A This is an XOR!

25. Comparison Total transistor count: 8 2 inverters=4 transistors Total transistor count: 8 4 inverters=8 transistors Total transistor count: 16

26. A Complex Function Using TG and a Standard Cell Hint! Follow the NMOS side of the transmission Gate NAND

27. RC model for CMOS Transmission Gate

28. Vin = 0V Cut-off SAT Linear SAT The parallel resistance is relatively constant

29. Vin=VDD Linear SAT SAT Linear The parallel resistance is relatively constant

30. Estimate the TG Resistance(Vin=VDD) Cutoff Approximately 12.5 KOhms/Square. Since the NMOS will be off as VS approaches VDD-VT. The average is resistance is 25 KOhms/Square SAT SAT Linear RTG(Vin=VDD)=RN||RP=2REQN||REQP =2REQN||2.4 REQN=1.1REQN Approximate as a pull-up with 30 KOhms/Square. For a unit size device, the resistance is 30 Kohms. For unit device both NMOS and PMOS

31. Estimate the TG Resistance (Vin=GND) Approximate NMOS as a pull-down with 12.5 KOhms/Square. For a unit size device, the resistance is 12.5 Kohms. Cut-off SAT Linear SAT Approximate PMOS 30 KOhms/Square. Since the PMOS will be off as VS approaches |VTP|. The average is resistance is 60 KOhms/Square RTG(Vin=GND)=RN||RP=REQN||2REQP =REQN||4.8 REQN=0.83 REQN =REQN For unit device both NMOS and PMOS

32. Resistance of TG • Vin(VDD)=1.1 REQN=REQN • Vin(GND)=0.83 REQN=REQN • The TG is approximately REQN regardless of rising or falling conditions. • To account for non unity devices: RTG=REQN(L/W)

33. Identification of Various Capacitances

34. Cgs,CgdandCgb Cg in series with Cj Gate:-Q Under SiO2:Q Channel almost from source to drain Channel extends from source to drain C(0V)=0.5Cg

35. Capacitance of the “OFF” Transmission Gate • CGS and CGD for both NMOS and PMOS are Off when the transmission gate is OFF! • The input and output capacitances are due to the junction capacitances of the n-channel and p-channel devices. Cin=Cout=Ceff(WN+WP)

36. Estimate the TG Capacitance (Vin=VDD) Cutoff SAT SAT Linear Input: {(2/3+0) +(1/2+0)}/2=3.5/6 Output: {(0+2/3)+(1/2+0)}/2=3.5/6

37. Estimate the TG Capacitance (Vin=GND) Cut-off SAT Linear SAT Input: {(0+1/2)+(2/3+0)}/2=3.5/6 Output: {(0+1/2)+(2/3+0)}/2=3.5/6

38. Hodges Assumption Assumption: the devices are assumed to be in the linear region. The total input and output capacitances are equal can be calculated as Cin=Cout=Ceff(WN+WP)+0.5(CgWN+CgWP)=Ceff2W+CgW Assume that WN and WP