Sebastian Loeda BEng(Hons)

1. Sebastian Loeda BEng(Hons) The analysis and design of low-oversampling, continuous-time  converters and the effects of analog circuits on loop stability and performance

2. Background Low oversampling, continuous-time  converters Loop delay effects Loop delay compensation by optimization Integrator circuit response finite DC gain Integrator circuit response high frequency pole Conclusion Future work Overview The analysis and design of low-oversampling, continuous-time  converters and the effects of analog circuits on loop stability and performance:

3. Introduction • A/D converter bottleneck to any sensor system • Particularly true for radar •  conversion achieves high-resolution with: • Oversampling (error averaging), • Limited by technology and bandwidth (here is low) • Feedback (quantization noise shaping) • Limited by the order of H(s), and may be unstable!

4. Analysis of CT  • Challenge due to mix of DT and CT • Create a DT model of the noise response • Model the quantization noise transfer function (NTF) • NTF(z) = 1/(1+H(z)) • Mapping cannot be an approximation!

5. Poles and zeros of NTF(z)

6. Loop delayNTF(z)

7. Loop delay SNR

8. Optimizer SNR Stability + a [ n ] y [ n ] S H (z) - NTF(z) Design-by-optimization

9. Loop delay τ compensationResonator H(s) – fixed poles

10. Loop delay τcompensationFree poles of H(s)

11. Resonator Vs Free poles of H(s) • Two regimes • Resonator optimum for low values of τ (~ 0.2) • Real polesoptimum for moderate values of τ • But lose noise notch • Unusual! • What about H(s)?

12. Ideal integrator model in H(s)large OSRs H(s)

13. Realistic integrators • Finite DC gain • High frequency poles and zeros • What is the impact of circuits on the loop performance and stability for low OSR?

14. Illustrative example:Integrator model to second order (ω2 proportion of sampling frequency)

15. Effects of finite DC gainNTF(z) Start: 100dB End: 0dB

16. Effects of finite DC gain SNR

17. Effects of second pole ω2NTF(z) Start: 10fs Hz End: 0.5fs Hz

18. Effects of second poles ω2 NTF(z) (altogether)

19. Effects of second poles ω2SNR

20. Can cope with loop delay Use of real poles of H(s) DC has a limited effect As long as it is kept reasonably high But note 3rd unusually sensitive ω2 is very important! Gets worse with low OSR Only one pole considered for illustrative purposes! First integrator stage is critical Wide bandwidth required but Must be low noise! The later the stage the lesser the effect Third a bit more sensitive than expected due to feedback in H(s), i.e. zeros of NTF(z) Summary

21. With low OSRs, cannot design a CT  without taking into consideration the integrator circuits’ response! Compensation Add zeros in In(s) What are the optimal zero positions? Mitigate circuit effects by optimising the model Expect similar mitigation seen for loop delay Advantages of design-by-optimization Optimum has zero matrix jacobian, i.e. robust Add circuit design criteria as optimization constraints (e.g. bound component sizes) Caveat: Depends on how well characterised the technology is Conclusions

22. Achievements Generalised the mapping for Any H(s) DAC shape and timings OSR Fast, general and accurate Essential for more sophisticated integrator/DAC models Assess the impact of circuits on CT  with a z-domain model Developed a design-by-optimization technique Future aims Create integrator models from realistic circuits Optimise directly on component values Cascaded CT  Practical advantages Increase performance out of good integrator circuit Reduce cost with primitive integrator Future work

23. Qs & (hopefully) As Thank you!