Efficient Static Compaction Algorithms for Combinational Circuits Based on Test Relaxation

1. Efficient Static Compaction Algorithms for Combinational Circuits Based on Test Relaxation Yahya E. Osais Advisor: Dr. Aiman H. El-Maleh Members: Dr. Sadiq Sait & Dr. Allaeldin Amin Dept. of Computer Engineering KFUPM 11-Oct-03

2. Outline • Motivation. • Research problems & contributions. • Taxonomy of static compaction algorithms. • Test vector decomposition. • Independent fault clustering. • Class-based clustering. • Test vector reordering. • Conclusions & future research. yosais

3. Motivation • Rapid advancement in VLSI led to SoC. • Testing SoCs requires large amount of data. • Impact on testing time & memory requirements of test equipment. • Challenges: • Reduce amount of test data. • Reduce time a defective chip spends on a tester. yosais

4. Research Problems • Static compaction for combinational circuits. • Reduce the size of a test set as much as possible. • Test vector reordering for combinational circuits. • Steepen the curve of fault coverage vs. number of test vectors. yosais

5. Contributions • Taxonomy of static compaction algorithms. • Test vector decomposition. • Test vector can be eliminated if its components can be moved to other test vectors. • Efficient static compaction algorithms. • IFC • CBC • Efficient test vector reordering algorithm. • Solutions to time and memory bottlenecks. yosais

6. Taxonomy of Static Compaction Algorithms Static Compaction Algorithms for Combinational Circuits Redundant Vector Elimination Test Vector Modification Test Vector Addition & Removal Essential Fault Pruning Set Covering Essential Fault Pruning Test Vector Reordering Merging Based on ATPG Test Vector Decomposition Based on ATPG Based on Raising Based on Relaxation IFC CBC Graph Coloring yosais

7. Test Vector Decomposition (TVD) • Decompose a test vector into its atomic components. • Employ relaxation per a fault. • tp = 010110 & Fp = {f1,f2,f3} • (f1,01xxxx) • (f2,0x01xx) • (f3,x1xx10) • Compaction modeled as graph coloring. yosais

8. Independent Fault ClusteringPreliminaries • Two faults are independent if they cannot be detected by a single test vector. • Two faults are compatible if their components are compatible. • A set of faults is independent (IFS) if no two faults can be detected by the same test vector. • A set of faults is compatible (CFS) if all faults can be detected by the same test vector. yosais

9. Independent Fault ClusteringAlgorithm Description • Fault simulate T without fault dropping. • Match essential faults: • Extract atomic component cf from t. • Map to cf CFS. • Find IFSs. • Match remaining faults: • Extract atomic component cf from t Tf. • Map cf to CFS. yosais

10. Independent Fault ClusteringIllustrative Example yosais

11. Independent Fault ClusteringIllustrative Example IFS1={f1,f9} IFS2={f2} yosais

12. Class-Based ClusteringPreliminaries • Conflicting Component (CC) A component c of a test vector t belonging to a test set T is called a CC if it is incompatible with every other test vector in T. • Degree of Hardness of a Test Vector A test vector is at the nthdegree of hardness if it has n CCs. • Class of a Test Vector A test vector belongs to class k if its degree of hardness is k. yosais

13. Class-Based ClusteringPreliminaries • Movable CC A CC ci is movable to a test vector t if the components in t incompatible with cican be moved to other test vectors. • Candidate Test Vectors Set of test vectors to which the CC ci can be moved. • Potential Test Vector A test vector whose CCs are all movable. yosais

14. Class-Based ClusteringAlgorithm Description • Fault simulate T without fault dropping. • Generate atomic components. • Remove redundant components using fault dropping simulation. • Classify test vectors. • Process class ZERO test vectors. • Re-classify test vectors. • Process class ONE test vectors. • Re-classify test vectors. • Process class i test vectors, where i > 1. yosais

15. Class-Based ClusteringComponent Generation • For every test vector t: • For every fault detected by t: • If f is essential • Extract atomic component cf from t. • Else • Decrement the number of test vectors detecting f by one. Component of a fault is extracted from a test vector that detects a large number of faults. yosais

16. Blockage value of component ci Number of class ZERO test vectors blocked when ci is moved to tj. Class-Based ClusteringBlockage Value yosais

17. Class-Based ClusteringBlockage Value • Components of a test vector whose blockage value is ZERO can be moved without blocking any class ZERO test vector. • Blockage value MUST be updated after moving components. • Update Rules: • If Scomp of a component is modified. • If a test vector receives new components. • If ci is in conflict with cj, Scomp(cj) modified, and Scomp(cj) = 1. yosais

18. Class-Based ClusteringIllustrative Example yosais

19. f7 f6 Class-Based ClusteringIllustrative Example yosais

20. f4 f5 f1 Class-Based ClusteringIllustrative Example yosais

21. Class-Based ClusteringIllustrative Example yosais

22. Algorithm: Rorder Using non-fault dropping fault simulation, set of all faults detected by each test vector is recorded. Repeat the following steps until no test vector is left in T: Select a test vector tifrom T such that ti detects the largest number of faults. Remove ti from T and append ti to the end of the ordered test set T*, which is initially empty. For each test vector tj in T, remove the faults detected by tifrom the set of faults detected by tj. Return T*. ● Fault simulation without fault dropping is time consuming. ● Memory requirement is high since all faults detected by every test vector are recorded. Test Vector ReorderingBottlenecks yosais

23. Test Vector ReorderingRecently Proposed Solution • Double detection fault simulation • A fault is dropped once it is detected twice. • Significant reduction in fault simulation time. • Not all faults are considered by a test vector. • Memory is always 2xF. • Impact on quality of final test sets • If average number of test vectors detecting a fault is much greater than two. yosais

24. Test Vector ReorderingOur Proposed Solution to Time Problem • Use of CRItical Path Tracing (CRIPT) as a fault simulator. • Cost of fault simulation without dropping is the same as that of fault simulation with dropping. • Experimental results reported by the inventors show that CRIPT is faster than concurrent fault simulation. • CRIPT does not solve the memory problem although it considers less faults. yosais

25. Test Vector ReorderingOur Proposed Solution to Memory Problem • For i = 1 to n: • Run CRIPT. Do not store faults. Store only the number of faults detected by every test vector. • Select the best m test vectors. • Drop all faults detected by the selected test vectors. • Run algorithm Reorder. Use CRIPT as a fault simulator. yosais

26. Experimental ResultsBenchmark Circuits yosais

27. Experimental ResultsResults by RM, GC, and IFC yosais

28. Experimental ResultsResults by RM, GC, and IFC • GC computes smaller test sets. • As much as 11.9% smaller compared to RM. • 1% for c2670; 9.5% for s38584f; 11.9% for s4863f. • Results by IFC are better compared to RM & GC. • Improvement over RM: 3% for s208.1f – 37.5% for s38584f • Improvement over GC: 1.4% for s3384f – 31% for s38584f • Runtime of IFC is better than that of GC. yosais

29. Non-dropping fault simulation for large circuits. Experimental ResultsSources of Time Consumption in IFC • Building IFSs. • Matching non-essential faults. yosais

30. Experimental ResultsResults by Iterative IFC yosais

31. Experimental ResultsResults by Iterative IFC • Improvement over RM: 3% - 46.6% e.g. 35.8% for s38417f • Improvement over IFC: 1.6% - 17.2% e.g. 14.5% for s38584f yosais

32. Experimental ResultsResults by CBC (ROF+RM) yosais

33. Experimental ResultsStatistics about Test Sets yosais

34. Experimental ResultsResults by CBC (ROF+RM) • Maximum reduction is 34%. • 2.5% for c3540; 23.5% for s38417f; 34% for s38584f. yosais

35. Non-dropping fault simulation for large circuits. Experimental ResultsSources of Time Consumption in CBC • Component generation. • Component elimination. • Blockage value computation. yosais

36. Experimental ResultsResults by CBC (ROF+IFC & ROF+Iter_IFC) yosais

37. Experimental ResultsResults by CBC (ROF+IFC & ROF+Iter_IFC) • ROF+IFC+CBC • Maximum reduction is 23.5%. • 16% for s38417f; 23.5% for c5315. • ROF+Iter_IFC+CBC • Maximum reduction is 18.6%. • 7.7% for s9234.1f; 18.6% for c5315. • ROF+IFC+CBC vs. ROF+RM+CBC • 1.1% - 18% • ROF+Iter_IFC+CBC vs. ROF+RM+CBC • 3% - 26.3% • ROF+Iter_IFC+CBC vs. ROF+IFC+CBC • 1.3% - 14.3% yosais

38. Effect of non-dropping fault simulation on the performance of TVR procedures. Experimental ResultsRuntimes spent by reordering procedures ● In Greedy, fault simulation is performed using HOPE. ● In CPT, fault simulation is performed using CRIPT. ● DD is run for four iterations. ● In CPT+, n = 4 & m = 4. yosais

39. Experimental ResultsMemory Required for Circuits yosais

40. Experimental ResultsFault Coverage Curves for s5378f yosais

41. Experimental ResultsFault Coverage Curves for s38417f yosais

42. Experimental ResultsEfficiency of Reordering Procedures yosais

43. Experimental ResultsEfficiency of Reordering Procedures yosais

44. Conclusions & Future Research • Contributions • Taxonomy of static compaction algorithms for combinational circuits. • Test vector decomposition. • Efficient static compaction algorithms. • IFC • CBC • Efficient test vector reordering algorithm. • Future Work • Investigate the impact of CRIPT & DD on the quality of compacted test sets. • Consider reducing the complexity of non-essential fault matching in IFC. • Improve the current implementation of building the IFSs. • Consider improving the time consuming phases in CBC. yosais

45. Publications • Aiman H. El-Maleh and Yahya E. Osais, "Test Vector Decomposition-Based Static Compaction Algorithms for Combinational Circuits", ACM Transactions on Design Automation of Electronic Systems, Special issue on VLSI Testing, pp. 430-459, vol. 8, issue 4, Oct. 2003. • Yahya E. Osais and Aiman H. El-Maleh, "A Static Test Compaction Technique for Combinational Circuits Based on Independent Fault Clustering", To appear in Proc. of the 10th IEEE Int'l Conference on Electronics, Circuits, and Systems, Dec. 2004. • Aiman H. El-Maleh and Yahya E. Osais, "A Class-Based Clustering Static Compaction Technique for Combinational Circuits", Submitted to ISCAS 2004. • Aiman H. El-Maleh and Yahya E. Osais, "On Test Vector Reordering for Combinational Circuits", Submitted to ISCAS 2004. yosais

46. Thank you yosais

47. Class-Based ClusteringBlockage Value • Technique is NOT exact. • Although v1 has a ZERO blockage value, it blocks v2. yosais

48. Worst-Case AnalysisMethodology • Test set, fault list, and circuit structure are given as inputs. • NT = No. of test vectors in given test set. • NPI = Size of a test vector. • NF = Number of faults in given circuit. • NG = Number of gates in given circuit. • Logic simulation of a test vector requires O(NG) basic operations. • Fault simulation of a test vector for a single fault requires O(NG) basic operations. yosais

49. Worst-Case AnalysisSpace Complexity of IFC O(NT(NF+NPI)) yosais

50. Worst-Case AnalysisSpace Complexity of CBC O(NF(NT+NPI)) yosais