GL1 Timing: Clock and Trigger Transmission and Implementation

1. The GL1 - vGTM diagram Clock GL1 The Local-Level 1’s provide input to the GL1 LL1 LL1 LL1 LL1 Granule Granule Granule Granule … vGTM vGTM vGTM vGTM FEM FEM FEM FEM FEM FEM FEM FEM FEM FEM FEM FEM FEM FEM FEM FEM Busy Busy Busy Busy The vGTMs transmit clock and trigger info to their front-ends They are aware of their granule’s busy state The GL1 transmits clock and trigger decision to the vGTMs GL1/Timing

2. What needs to be done (hardware) Design 8-transceiver breakout board to get full complement of 14 transceivers Outfit the units in hand with the actual connector (1 of 6 instrumented) Breakout board 8 more SFPs 6 SFPs Do we need sub-1/2 clock timing delay hardware on those? Under discussion GL1/Timing

3. What needs to be done (firmware) GL1 Granule vGTM The core firmware (20% strawman implementation exists) Implement (fractional) scaledowns Accept external (RHIC or other) clock, fiducial tick Accept data from LL1s (presumably TLK transceivers) Devise a way to send data to DAQ (crude strawman via network in place, change to “LL1 way” – presumably jSEB2) Accept aggregated busy from GTM board Provide “n” trigger inputs, parameterized Busy Further develop core firmware (larger repeat counts, etcetc) Implement multi-event buffering Implement busy propagation Accept external (RHIC or other) clock Accept trigger data from GL1 Devise a way to send data to DAQ Expand configuration space as needed Interface w/ calorimeter timing board once available GL1/Timing

4. TPC and Calorimeter This exists! Same for FELIX-based MVTX vGTM TPC-FEE FELIX This awaits the availability of the clock distribution board vGTM CalorimeterDigitizer Crate Different vGTM firmware for the 2 systems Very different clock distribution Clock distribution board GL1/Timing

5. GL1 readback in RCDAQ -- Event 2 Run: 4 length: 28 type: 1 (Data Event) Accept vector 1 Beam Clock 10533763685 T0 raw 1 T0 live 1 T0 scaled 1 T1 raw 0 T1 live 0 T1 scaled 0 -- Event 3 Run: 4 length: 28 type: 1 (Data Event) Accept vector 1 Beam Clock 10764577311 T0 raw 2 T0 live 2 T0 scaled 2 T1 raw 0 T1 live 0 T1 scaled 0 Two triggers accepted on input 0 11 out of 13 accepted on input 0 Two arrived while DAQ was busy -- Event 12 Run: 4 length: 28 type: 1 (Data Event) Accept vector 1 Beam Clock 12539380911 T0 raw 13 T0 live 11 T0 scaled 11 T1 raw 0 T1 live 0 T1 scaled 0 This is using the network port. Likely not good enough for 15KHz GL1/Timing

6. Highlight: vGTM protocol to TPC The clock/trigger data are transmitted at 6x the beam clock speed (~56MHz) 6 x 16bit of data transmitted per RHIC beam crossing 8 Mode bits (“what to do at this RHIC crossing”) 40 bits (out of 64) of the global beam clock counter Trigger accept and misc. housekeeping info 3 user bits (currently unused) RHIC Beam Clock GL1/Timing

7. Highlights: beam clock in streaming data 0000000 0085 bcae 000a 0048 004c 004c 004b 004b 004c 0000276 008d bcae 000a 004a 004c 004d 004e 004c 004b 0000552 0095 bcae 000a 004b 004a 004c 004f 004c 004c ... 0037812 00ee bcae 000a 003f 003d 003c 0042 0041 0040 0038088 00f6 bcae 000a 004c 0049 004a 004a 004b 004b 0038364 00fe bcae 000a 0050 0051 0053 0052 0051 0051 0038640 0043 e117 0006 0042 0044 0047 0045 0046 0042 0038916 004b e117 0006 0042 0044 0044 0043 0042 0044 0039192 0053 e117 0006 004c 0050 0052 004e 004f 004b ... 0108468 00ca e117 0006 0051 0051 004e 004e 004e 0051 0108744 00d2 e117 0006 0053 0055 0053 004e 004d 0050 0109020 00da e117 0006 0052 0053 004f 0050 0052 0052 TPC data triggered with GTM 0109296 0025 e2f8 000a 0042 0042 0043 0043 0046 0042 0109572 002d e2f8 000a 004a 004a 0046 0049 0048 0049 0109848 0035 e2f8 000a 0053 0050 004f 0051 0054 0056 ... 0179124 00ee e2f8 000a 0042 0040 0040 0040 0042 0040 0179400 00f6 e2f8 000a 004e 004c 0048 004a 004a 0049 0179676 00fe e2f8 000a 0050 0053 0052 0050 0054 0051 0179952 0043 9693 000e 0042 0046 0046 0043 0046 0042 0180228 004b 9693 000e 003e 0041 0043 0046 0042 0042 0180504 0053 9693 000e 004b 004e 004e 004a 004b 004e ... 0249780 00ca 9693 000e 0050 0051 0050 0050 004d 004f 0250056 00d2 9693 000e 0050 0050 0052 0053 0054 0053 0250332 00da 9693 000e 0053 0053 0053 0055 0056 0052 0250608 0043 d5b8 000e 0044 0046 0043 0044 0044 0042 0250884 004b d5b8 000e 0044 0044 0042 0044 0042 003e 0251160 0053 d5b8 000e 004d 004c 004a 004d 004e 004c Sampa 5, channel 10 Sampa 5, channel 18 Sampa 5, channel 26 … GL1/Timing

8. Summary • Prototype GL1 implementation is functional • Almost complete vGTM functionality interfaced with the FELIX front-ends • Data available for alignment tests and event building software (beam clock data embedded) • Data taking in TPC lab setting routinely with vGTM support • Early version of the GL1 DAQ interface implemented (readback of per-event trigger decision data) • GL1 and Timing ready for PD-2/3 approval. GL1/Timing

9. Back Up GL1/Timing

10. Felix’s view of the GTM data 16 bits transmitted per 6x Beam Clock edge 6x Beam Clock GL1/Timing

11. Activities over the next few months • Working towards a complete GL1 implementation • Number of triggers (currently 2 because of two convenient Lemo inputs) as parameter • Finalize APIs for GL1 configuration • Look into a “one-board” system - implement GL1 and vGTM in one FPGA for lab and beam tests • Interface to GL1 - GTM boards via fiber • Implement “fractional scaledowns” – integer currently but we want like ”2 out of 3” • Setting up a “multiple systems test” (likely calorimeter + TPC hardware) • Combine different flavors of hardware • Demonstrate proper alignment/reconstruction of events and GL1 info • This is awaiting the aforementioned clock master board and assorted firmware GL1/Timing

12. Schedule Drivers GL1/Timing