PLACEMENT USING DON’T CARE WIRES

1. PLACEMENT USINGDON’T CARE WIRES Fan Mo Don’t Care Wire Group: P.Chong, Y-J.Jiang, S.Singha and R.K.Brayton

2. OUTLINE • Design flow overview • What is don’t care wire? • What is our macro-cell placer? • How to use don’t care wires in placement? • Experiment, results and conclusion

3. DESIGN FLOW OVERVIEW Netlist PLA-based Decomposition pins with wire choices SPFD-based Don’t Care Wire Generation Placement based on Wire Choices wire choice made Resynthesis Final Placement Cell area and net connection determined Layout

4. Yamashita and etc., “A new method to express functional permissibility for LUT based FPGAs and its applications”, ICCAD96 Brayton, “Understanding SPFDs: A new method for specifying flexibility”, IWLS97 Sinha and Brayton, “Implementation and use of SPFD”, ICCAD98 YA Z-space y1 y4 y2 y5 YB Y-space y2 y4 y3 YA YB YC y5 YC y1 y5 y3 y4 Primary Inputs SPFD

5. 0 need SPFDYA need SPFDYC need SPFDYB Y-space provide at least SPFDYC provide at least SPFDYA provide at least SPFDYB 7 6 2 10 1 9 4 3 5 8 SPFD Each input pin of a node needs information described by its SPFD, and some other non-TFO nodes provide the required information.

6. DON’T CARE WIRES Denition 1Given a set of sets of nodes R={Rk}, a selection is an ordered set of nodes {1, … , |R| } such that kRk. Denition 2A set of sets R={Rk} is compatible if for each selection, there exist logic functions at each node such that the implied netlist for that selection can implement the specications at the primary outputs. TheoremAny set of sets of nodes {Rk} satisfying 1. For any selection, the resulting netlist is acyclic, and 2. ’Rk SPFDk SPFD’ is compatible.

7. ex() ex(’ )   R DON’T CARE WIRES Procedure (Constructing a compatible set, but still acyclic network) 1. Starting from the outputs and proceeding in a backward topological order, for each node  in the network, and each of its input pins, , assign SPFDs, SPFD and SPFD so that the required information is supplied. Once this is done, each SPFD represents the set of minterms which must be distinguished by that node or pin. 2. Initialize for each node , ex()={}TFO and for each input pin,  of , let R={’ }, where ’ is the initial choice of source for pin . R will eventually represent the set of alternate wires for . 3. Starting from the inputs and proceeding in some topological order, at each node , do the following: (a) Let C =~ex() (b) For each fanin wire  of : # Find an ’ C such that SPFD SPFD’ . # Include ’ in R , R = R  {’ } . # Update ex(’ ) = ex()ex(’ ). (to avoid cycles.) # This continues until no more nodes can be added to R . ’

8. USE DON’T CARE WIRES IN PLACEMENT Wire choice interleaves cell placement • Based on current placement, determine which wire among the choice set is chosen in terms of wire length reduction. • Based on current netlist, determine the movement of the cells.

9. AWC PHASE I • For each pin with alternate wires, temporarily disconnect it from the current net. • For each net form the bounding boxes of the currently connected pins. These partial bounding boxes form a lower bound on the total wire length. • For each pin with alternate wires, if its pin position is inside one of the partial bounding boxes for its candidate wires (the original wire plus its alternates), assign it to that net. No increase has been caused by this, and hence the partial assignment seen so far must be part of an optimum assignment. • For each remaining pin with alternate wires, compute the “delta” costs if it is assigned to each of the candidate nets. There is a net assignment which increase the total net length by the least amount. Choose this assignment and update the chosen net. • Continue last step until all pins have been assigned.

10. AWC PHASE I

11. AWC PHASE II • For each pin which is an extreme of the bounding box of its currently assigned net, temporarily release it from its assignment, and compute the best net to put it in and its delta decrease cost in doing this. Note that the delta decrease is nonnegative. • Choose the pin with the maximum delta decrease and reassign the pin to the new net. • Repeat the above steps until the best delta is 0.

12. AWC PHASE II

13. AWC • After PHASE I, there may be pins that can be moved to different nets to improve the total cost. • During PHASE II, a pin may be reassigned more than once. To speed up the process, one may want to “lock” a pin once it is reassigned once. • After PHASE II (with no locking), the solution is locally optimal, in that there is no pin which can be moved to a new net such that the total cost is decreased. However, there might be a set of pins that can be reassigned all at once which decreases the cost. • Chong and etc., “Don’t care wires in logic/physical design”, IWLS00

14. FORCE-DIRECTEDMACRO-CELL PLACER • Iterative so that wire choice can be merged into the placement. • Incremental so that final placement can start from the layout done after wire choice instead of starting from scratch. • Need to handle maro-cell, not only standard cell. Iterative and Incremental Standard cell design Macro-cell design • Quinn and Breuer, “A Forced Directed Component Placement Procedure for Printed Circuit Boards”, IE3 Trans.-CAS79 • Eisenmann and Johannes, “Generic global placement and floorplanning”, DAC98

15. FORCE-DIRECTEDMACRO-CELL PLACER • Short Total Wire Length Attractive forces applied on connected cells. • Small Area Cells are dragged by attractive forces. • Cell Orientation and Aspect Ratio (for soft cell) Gain function describing the relation between force reduction and cell orientation and shape. • Eliminate Overlapping Density field method. Make an evenly distributed layout. Also use pads to pull cells apart. • Iterative It should be. AWC can be easily merged in the placer. • Run Time We seek more speed up by using a new wire model. • Other Interesting Features Wire congestion estimation. Pad positioning.

16. Star[s] Cell[1] Cell[2] Chip Pad[1] Pad[2] PLACER ATTRACTIVE FORCE Using star wire model instead of clique wire model. About 30% saving. k: net weight; Pc: cell location; OT: terminal offset; Ps: star location

17. [ ] BRTX c [ ] MRTY c ] c [ BRTY ] c [ ] c [ MLBX MRTX ] c [ ] MLBY c [ BLBY BinSize [ ] BLBX c PLACER DENSITY FIELD

18. PLACER FORCE EQUATIONS

19. S N W E H T V R PLACER CELL ORIENTATION Gain of taking an orientation:

20. PLACER CELL ASPECT RATIO new width/height ratio:

21. PLACER ORIENTATION vs ASPECT RATION ORIENTATION ASPECT RATIO discretecontinuous find a better one find the best easy to computemore run time for both hard/soft cellonly for soft cell better in earlier stage better in later stage

22. D D B B A A C C PLACER PAD POSITIONING Attract force one dimensional density field and filling force

23. L w BinSize PLACER WIRE CONGESTION ESTIMATION 1 Area paid for connections to star in terms of contribution to density field.

24. PLACER WIRE CONGESTION ESTIMATION 2 #W-,#W+ : the no. of wires go two opposite directions. w : wire pitch e=left,bottom,right,top cell edge; KOC: the constant keepout distance Area paid for the connections to the terminals in terms of keepout distance of cell edges.

25. 1/4 1/3 1/4 1/3 1/2 S 1/4 1/4 1/4 1/4 1/4 1/4 1/3 1/3 1/2 1/2 S S 1/3 1/4 0 1/4 1/3 1/2 1/3 1/3 1/4 1/4 1/4 1/4 1/4 1/4 1/3 1/3 1/2 1/2 1/2 1/3 1/4 1/3 1/4 1/3 1/2 1/2 1/3 1/3 1/4 1/4 1/4 1/4 1/4 1/4 1/3 1/3 1/2 1/3 1/4 1/3 1/4 T 1/2 1/2 1/3 1/3 1/4 1/4 1/4 1/4 1/4 1/4 T T PLACER WIRE CONGESTION ESTIMATION 3 No obstruction Obstruction, not fully blocked Obstruction, fully blocked Area paid for the wiring between star and terminal in terms of contribution to density field.

26. 1 CELL AREA RATIO CHIP DENSITY 0 STAGE I STAGE II STAGE III INITIALIZE EXPLODE CLEAN UP PLACEMENT FLOW Initialize_and_ZeroSize_Cells(); SetCellsSizeZero(); loop Stage1IterationNumber { ComputeAttractiveForces_and_Move_Stars(); ComputeAttractiveForces_and_Move_Cells(); AWC( ); DetermineChipBoundary(); ComputeAttractiveAndFillingForce_and_Slide_Pads(); } explode(); 1 loop Stage2IterationNumber { IncreaseCellSize(); ComputeAttractiveForces_and_Move_Stars(); ComputeAttractiveForces_Cells(); ComputeKeepOutDistance_for_Cells(); ComputeBinDensity(); ComputeFillingForces_Cells(); MoveWithLimit_Cells(); ComputeOrientationGain_and_ChooseOrientation_for_Cells(); AWC( ); DetermineChipBoundary(); ComputeAttractiveAndFillingForce_and_Slide_Pads(); } Resynthesis( ); UpdateCellInformation( ); resynthesis 2 while (exist bin, density > densityThreshold) { ComputeAttractiveForces_and_Move_Stars(); ComputeAttractiveForces_Cells(); ComputeKeepOutDistance_for_Cells(); ComputeBinDensity(); ComputeFillingForces_Cells(); MoveWithLimit_Cells(); ComputeSoftCellAspectRatio(); DetermineChipBoundary(); ComputeAttractiveAndFillingForce_and_Slide_Pads(); } CleanUp(); 3

27. EXPERIMENT break the acyclic constrain Characterization of Examples number of pins with alternates the percentage of such pins among all pins average alternate number of these pins

28. EXPERIMENTAL RESULTS Average improvement: regular 5.1%, re-synthesis 3.9% max 5.4%

29. EXPERIMENTAL RESULTS Average improvement: 4i2o 7.0%, 1i1o 8.2%

30. CONCLUSION • Synthesis-interactive placer. AWC. • Improvement in terms of total wire length and area. • Macro-cell placement algorithm, handling cell orientation, cell aspect ratio and pin(pad) position. Also with wiring estimation.