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DFEE status report

DFEE status report. P. Musico, M. Pallavicini , F. Pratolongo I.N.F.N. Genova. Contents. Activities since Palermo meeting Test DFEE prototype Continue developing IEFE, Interface to Euso Front End. DFEE protoype on test board. Magnified. Open chip in its case.

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DFEE status report

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  1. DFEE status report P. Musico, M. Pallavicini, F. Pratolongo I.N.F.N. Genova

  2. Contents • Activities since Palermo meeting • Test DFEE prototype • Continue developing IEFE, Interface to Euso Front End

  3. DFEE protoype on test board

  4. Magnified Open chip in its case

  5. Analog test output (1 channel) 100 ns wide pulse 10 ns wide pulse

  6. DFEE prototype tests (I) Threshold scan with Input pulse corresponding to ½ photoelectron

  7. DFEE prototype tests (II) Threshold scan with Input pulse corresponding to 1 photoelectron

  8. Gain uniformity : 16 channels Gain uniformity derived from threshold scan 2 pe 1 pe ½ pe

  9. Power needs measurements Total power with no clock: 9.9 mW  0.6 mW/channel • We have carefully measured power needs • Chip uses 3 power lines, 3.3 V each : VADD, VCDD, VDD Measured currents (no digital clock): IADD =1.1 mAICDD=1.4 mAIDD=0.5 mA With continuous clock, of course things get worse: Next chip generations will probably not use continuos clock

  10. Future activity • Continue tests • Test digital functions (long job) • Interface DFEE to existing microcell • Build the first section of Euso focal surface! • Build IEFE and connect microcell to PC • Future design efforts • Start integration with AFEE • Implement possible new triggers • Groups of channels for triggering • Pattern recognition ? Need power, too early to say how much.Need also a big effort with TEO

  11. IEFE • In order to test all chip functions, a dedicated interface is needed. • Main features: • USB interface and 19 V laptop power supply (easy to use anywhere with a laptop) • Up to 8 chip handled in parallel. • Hardware interface (START, STOP and such) for fast timing sequences • Windows (and maybe Linux) based software interface • Block diagram designed. An engineer from Torino and one from Genova is working on the • Most of the functions will be handled by fully programmable devices • Remote re-programming via USB for multi-purpose use • Some logic analyzer functionalities included to handle macrocell logic signals, if needed. • It may become the standard testing tool for a microcell

  12. IEFE block diagram

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