Challenges in Robust Optimization of Digital Integrated Circuits

1. Challenges in RobustOptimization of DigitalIntegrated Circuits Chandu VisweswariahSystems and Technology GroupIBM

2. Outline • The scourge of manufacturing variability! • Two ways of dealing with variability in timing • Multi-corner static timing analysis • Statistical static timing analysis • Continuous robust optimization: the state-of-the-art • Discrete robust optimization: the state-of-the-art • Open challenges Analysis Optimization Chandu Visweswariah

3. Increasing and inevitable parametric variability Litho-induced variability Oxide thickness Random dopant effects* Interconnect CMP and RIE effects *D. J. Frank et al, Symp. VLSI Tech., 1999 Chandu Visweswariah

4. Shrink by • Statistical timing • Stochastic optimization • Design-for-manufacturing (DFM) techniques • Post-silicon tuning Best Case Unacceptable! Worst Case What variability does to performance Performance Technology generation Chandu Visweswariah

5. Classification of variability Variability Chip-to-chip,wafer-to-wafer,lot-to-lot,fab.-to-fab. Within chip Systematic Random Systematic Random “Best case” / “Worst case” “Early” / “Late” Chandu Visweswariah

6. WC late Within-chip “systematic” variation WC early BC late BC early Chip-to-chip variation Modeling of variability Individual Ring Oscillator Delay Mean Ring Oscillator Delay Chandu Visweswariah

7. Outline • The scourge of variability! • Two ways of dealing with variability in timing • Multi-corner static timing analysis • Statistical static timing analysis • Continuous robust optimization: the state-of-the-art • Discrete robust optimization: the state-of-the-art • Open challenges Chandu Visweswariah

8. (Deterministic) static timing analysis in its simplest form* a Node forevery pin • Simple one-pass traversal helps us find the longest and shortest paths in the timing graph • One backward traversal is used to compute Required Arrival Times (RATs) a z z  b Arc for everypin-to-pin transition b *R. B. Hitchcock Sr., G. L. Smith, D. D. Cheng, “Timing analysis of computer hardware,” IBM J. R&D, January 1982, pp. 100—105. Chandu Visweswariah

9. Comb. Comb. Comb. Verifying timing of setup tests early clock LF3 LF1 LF2 CF late data Robustness = Correlated variability in launch and capture paths Chandu Visweswariah

10. Comb. Comb. Comb. Verifying timing of hold tests late clock LF3 LF1 LF2 CF early data Chandu Visweswariah

11. Multi-corner timing • Chip-to-chip variation covered with multiple corners + margins • Within chip systematic covered by early/late split Temperature Voltage Process Chandu Visweswariah

12. Outline • The scourge of variability! • Two ways of dealing with variability in timing • Multi-corner static timing analysis • Statistical static timing analysis • Continuous robust optimization: the state-of-the-art • Discrete robust optimization: the state-of-the-art • Open challenges Chandu Visweswariah

13. a + c + MAX b a + c + MAX b Quick introduction to statistical timing • Deterministic • Statistical Chandu Visweswariah

14. Independentlyrandomuncertainty Deviation ofglobal sourcesof variation fromnominal values Sensitivities Constant(nominalvalue) Parameterized timing quantities* • All timing quantities are parameterized by the sources of variation • Correlation can be judged on-demand by inspection *C. Visweswariah, K. Ravindran, K. Kalafala, “First-order parameterized block-based statistical timing analysis,” TAU, February 2004, pp. 17—24*C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, S. Narayan, “First-order incremental block-based statistical timing analysis,” DAC, June 2004, pp. 331—336. Chandu Visweswariah

15. Statistical timing basics • Model all arc delays in “canonical” parameterized form • Represent all timing quantities in parameterized form • Delays, slews, guard times, ATs, RATs, slacks, PLL adjusts, constraints, CPPR adjusts • Propagate ATs through the timing graph in canonical form • Final timing results are available in canonical form • Automatically obtain sensitivity to sources of variation; taming these sensitivities improves robustness • Can project to single values (see next page) • Can plot as PDFs, CDFs, yield curves Chandu Visweswariah

16. Sample projections Chandu Visweswariah

17. Comparing multi-corner and statistical timing Chandu Visweswariah

18. Slack threshold Timing tests in this blue cube are fails Sensitivity threshold Robustness checking Chandu Visweswariah

19. Outline • The scourge of variability! • Two ways of dealing with variability in timing • Multi-corner static timing analysis • Statistical static timing analysis • Continuous robust optimization: the state-of-the-art • Discrete robust optimization: the state-of-the-art • Open challenges Chandu Visweswariah

20. Deterministic transistor sizing problem • “Analysis is done by devils, optimization by angels” • Typically applied to custom-designed circuits • Note that z and the ATs are variables of the optimization problem • are computed by adjoint sensitivity analysis in the time-domain Chandu Visweswariah

21. Statistical transistor sizing problem • The problem formulation is cleaner and easier (eliminates redundancies and degeneracies)! • This is because the (approximate) statistical max function is differentiable! • The big question is how to compute By adjoints, as before Chandu Visweswariah

22. Gradient computation* Imaginary cutset *J. Xiong, V. Zolotov, C. Visweswariah, “Incremental criticality and yield gradients,” Design Automation and Test in Europe (DATE), Messe Munich, Germany, pages 1130--1135, March 2008. Chandu Visweswariah

23. Results (maximize minimum of 4 slacks)* *D. K. Beece, J. Xiong, C. Visweswariah, V. Zolotov, Y. Liu, “Transistor sizing of custom high-performance digital circuits with parametric yield considerations,” Design Automation Conference (DAC), Anaheim, CA, June 2010. Chandu Visweswariah

24. Outline • The scourge of variability! • Two ways of dealing with variability in timing • Multi-corner static timing analysis • Statistical static timing analysis • Continuous robust optimization: the state-of-the-art • Discrete robust optimization: the state-of-the-art • Open challenges Chandu Visweswariah

25. The discrete optimization problem • Physical synthesis is used to construct most macros/units • Made up of library cells of various logic types and sizes (unlike in custom design) • Can handle large chunks of logic • Fully automated • Highly productive way of designing • Physical synthesis operates in a huge discrete space and carries the design from logic to shapes • “Changes” or “transforms” are applied on a list of gates/wires that have poor timing • The changes are evaluated by invoking the timer in an incremental manner Chandu Visweswariah

26. Synthesis transforms • Buffering or repeater insertion • Layer assignment • Gate sizing or repowering • Vt swapping • Cell movement • Inverter absorption / inverter decomposition • Cloning • Inverter / buffer deletion • Composition / decomposition Courtesy: Chuck Alpert Chandu Visweswariah

27. Buffering long nets Courtesy: Chuck Alpert Chandu Visweswariah

28. Buffering a net to reduce fanout (before) Courtesy: Chuck Alpert Chandu Visweswariah

29. Buffering a net to reduce fanout (after) Courtesy: Chuck Alpert Chandu Visweswariah

30. a e c d d f b Layer assignment a e c f b Courtesy: Chuck Alpert Chandu Visweswariah

31. a e c d d f b Gate sizing or repowering c a e b f Courtesy: Chuck Alpert Chandu Visweswariah

32. a e c d d f b High vt Vt swapping Regular vt Low vt a e c f b Courtesy: Chuck Alpert Chandu Visweswariah

33. a e c d d f b Cell movement a e c f b Courtesy: Chuck Alpert Chandu Visweswariah

34. a e c d f b g Inverter absorption / decomposition a e f b Courtesy: Chuck Alpert Chandu Visweswariah

35. Cloning S1 D1 P S1 D1 P D2 D2 S2 S2 P’ Courtesy: Zhuo Li / David Papa Chandu Visweswariah

36. Composition / decomposition w Out x w AOI nd2 B x Out nd2 A y nd2 C y nd2 C z z D D Courtesy: Louise Trevillyan Chandu Visweswariah

37. Variability-related challenges • Variability is handled by • A multi-corner static timer, or • A statistical static timer • This makes sign-off timing expensive! • Physical synthesis methods are not equipped to handle statistics • Of all the “changes” tried, only ~10% get accepted • Either • Use a fast/approximate timing mode and periodically update with sign-off timing • Work with sign-off timing but invoke incremental timing less often Chandu Visweswariah

38. Food for thought • This is an important optimization problem where heuristics rule and mathematical techniques have failed! • Heuristics are used to decide • Which parts of the design to optimize • Which optimizations to apply • In what order to apply these optimizations • When to accept uphill moves (if at all) • When to undo previously accepted moves (if at all) • When to stop or try something else Chandu Visweswariah

39. Some thoughts • Diagnostics that can be used to reduce the number of failed tries and/or “tune” heuristics • Process sensitivities • Try different changes depending on the ordering of sensitivities, the way a human would, for example: • Slew (rise/fall time) information • Fanout information • Logic complexity information Chandu Visweswariah

40. Outline • The scourge of variability! • Two ways of dealing with variability in timing • Multi-corner static timing analysis • Statistical static timing analysis • Continuous robust optimization: the state-of-the-art • Discrete robust optimization: the state-of-the-art • Open challenges Chandu Visweswariah

41. Open challenge • Plenty of progress on analysis with uncertainty • Recent work on continuous optimization in the face of variability • Could also be formulated as a 2-stage optimization to take into account post-manufacturing tuning • Challenge: How do we optimize large integrated circuits in a HUGE, discrete, multi-dimensional, highly constrained optimization space while triggering the incremental (statistical or multi-corner) timer as little as possible Chandu Visweswariah