Soft Error Rate Determination for Nanometer CMOS VLSI Circuits Fan Wang Vishwani D. Agrawal

1. Soft Error Rate Determination for Nanometer CMOS VLSI Circuits Fan Wang Vishwani D. Agrawal Department of Electrical and Computer Engineering Auburn University, AL 36849 USA 40th Southeastern Symposium on System Theory SSST'2008

2. Outline • Background • Problem Statement • Analysis • Results and Discussion • Conclusion SSST'2008

3. Motivation for This Work • With the continuous downscaling of CMOS technologies, the device reliability has become a major bottleneck. • The sensitivity of electronic systems can potentially become a major cause of soft (non-permanent) failures. • The determination of soft error rate in logic circuits is a complex problem. • It is necessary to analyze circuit reliability. However, there is no comprehensive work that considers all the factors that influence the soft error rate. SSST'2008

4. Strike Changes State of a Single Bit 1 0 Definition from NASA Thesaurus: “Single Event Upset (SEU): Radiation-induced errors in microelectronic circuits caused when charged particles [also, high energy particles] (usually from the radiation belts or from cosmic rays) lose energy by ionizing the medium through which they pass, leaving behind a wake of electron-hole pairs”. SSST'2008

5. source drain Impact of Neutron Strike on a Silicon Transistor neutron strike Strikes release electron & hole pairs that can be absorbed by source & drain to alter the state of the device + + - + + - - - Transistor Device • Neutron is a major cause of electronic failures at ground level. • Another source of upsets: alpha particles from impurities in packaging materials. SSST'2008

6. p p n n p n n p n p n Earth’s Surface Cosmic Rays Source: Ziegler et al. • Neutron flux is dependent on altitude, longitude, solar activity etc. SSST'2008

7. Problem Statement • Given background environment data • Neutron flux • Background energy (LET*) distribution *These two factors are location dependent. • Given circuit characteristics • Technology • Circuit netlist • Circuit node sensitive region data *These three factors depend on the circuit. • Estimate neutron caused soft error rate in standard FIT** units. *Linear Energy Transfer (LET) is a measure of the energy transferred to the device per unit length as an ionizing particle travels through material. Unit: MeV-cm2/mg. **Failures In Time (FIT): Number of failures per 109 device hours SSST'2008

8. Measured Environmental Data • Typical ground-level neutron flux: 56.5cm-2s-1. • J. F. Ziegler, “Terrestrial cosmic rays,” IBM Journal of Research and Development, vol. 40, no. 1, pp. 19.39, 1996. • Particle energy distribution at ground-level: “For both 0.5μm and 0.35μm CMOS technology at ground level, the largest population has an LET of 20 MeV-cm2/mg or less. Particles with energy greater than 30 MeV-cm2/mg are exceedingly rare.” • K. J. Hass and J. W. Ambles, “Single Event Transients in Deep Submicron CMOS,” Proc.42nd Midwest Symposium on Circuits and Systems, vol. 1, 1999. Probability density 0 15 30 Linear energy transfer (LET), MeV-cm2/mg SSST'2008

9. Occurrence rate Proposed Soft Error Model SSST'2008

10. X Y 1 Dout 0 τp 2τp Din Pulse Widths Probability Density Propagation fX(x) Delay τp fY(y) We use a “3-interval piecewise linear” propagation model • Non-propagation, if Din ≤τp. • Propagation with attenuation, ifτp < Din <2τp. • Propagation with no attenuation, if Din 2τp. Where • Din: input pulse width • Dout: output pulse width • τp : gate input output delay SSST'2008

11. Validating Propagation Model Using HSPICE Simulation • Simulation of a CMOS inverter in TSMC035 technology with load capacitance 10fF SSST'2008

12. Pulse Width Density Propagation Through a CMOS Inverter SSST'2008

13. Soft Error Occurrence Rate Calculation for Generic Gate SSST'2008

14. SER Results on Workstation Sun Fire 280R SSST'2008

15. SER Results for Inverter Chains SSST'2008

16. Result Comparison • The altitude is not mentioned for these data. • [1] R. R. Rao, K. Chopra, D. Blaauw, and D. Sylvester, “An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits," Proceedings of the conference on Design automation and test in Europe, pp. 164-169, 2006. SSST'2008

17. Conclusion • SER in logic and memory chips will continue to increase as devices become more sensitive to soft errors at sea level. • By modeling the soft errors by two parameters, the occurrence rate and single event transient pulse width density, we are able to effectively account for the electrical masking of circuit. • Our approach considers more factors and thus gives more realistic soft error rate estimation. SSST'2008

18. References [2] J. Graham, “Soft errors a problem as SRAM geometries shrink,“http://www.ebnews.com/story/OEG20020128S0079, ebn, 28 Jan 2002. [3] Wingyu Leung; Fu-Chieh Hsu; Jones, M. E., "The ideal SoC memory: 1T-SRAMTM," Proc.13th Annual IEEE International on ASIC/SOC Conference, pp. 32-36, 2000 [4] Report, “Soft Errors in Electronic Memory-A White Paper," Technical report, Tezzaron Semiconductor, 2004. SSST'2008