Low-power high-slew-rate CMOS buffer amplifier for flat panel display drivers

1. Low-power high-slew-rate CMOS bufferamplifier for flat panel display drivers ELECTRONICS LETTERS 16th February 2006 Vol. 42 No. 4 指導教授：林志明 所長 學 生：賴信吉 Email：S94662005@mail.ncue.edu.tw

2. Author S.K. Kim, Y.-S. Son and G.H. Cho (Division of Electrical Engineering, Department of Electrical Engineering and Computer Science (EECS), Korea Advanced Institute of Science and Technology (KAIST), 373-1, Guseong-dong Yuseong-gu, Daejeon 305-701, Republic of Korea)

3. Outline • Introduction • Proposed circuit • Experiment and results • Conclusions • Simulation by DIY

4. Introduction • The columns of flat display panels using liquid crystal displays (LCDs) and organic light emitting diodes (OLEDs) are heavily capacitive electronically. • As the display resolution increases, the load capacitance of one buffer increases, whereas the required settling time decreases. • A high-slew-rate buffer amplifier with low static power consumption is indispensable. • We present a newly developed buffer amplifier that consumes a very low static current and has a high slew rate.

5. Proposed circuit • NMOS-input stage → output PMOS MPPMOS-input stage → output NMOS MN • Folded cascode. • Symbol explanation. • Unit-gain buffer.

6. Feedback technology feedback

7. NMOS part IM7(A)=IM4(A)+IM10(A) and IM7(A)=IM8(A) k1 is the size ratio of M9(A) and M10(A) 0<k1<1

8. k3 is the size ratio of M5(A) and MP(N). k2 is the size ratio of M9(A) and M11(A) Note that by letting the constant current sources IM3(A) and IM4(A) be very small, the amplifier can be designed toconsume a very low static current.

9. The parameters that control the maximum sourcing or sinking current are vbp(n)2, the size of M7(A),and the size ratios of k2 and k3. • It should be noted that the preceding two parameters (vbp(n)2, M7(A)) can be designed independently of the static bias current. • The Early effect and mismatches of transistors are neglected.

10. Vin+ > Vin- (a*k1) (a) Vin+ < Vin- (b) (b) (b*k3)

11. Experiment and results • We manufactured the proposed buffer amplifier using a 0.35 μm CMOS process. • The proposed buffer has a possible slew rate higher than 10 V/μs for a load capacitance of1 nF almost independently of static currents as low as 1μA. • The steady-state errors between the input and output voltages were less than 10 mV in the entire operating region.

15. Conclusions • High-slew-rate buffer amplifier that has great potential for applications in flat panel displays. • A large current-driving capability by employing well-controlled positive current feedback loops and has control parameters for the maximum driving current.

16. Simulation by DIY

19. VOLTAGE OFFSET (10 mv)

20. Slew-Rate and Power

21. END THANKS!!