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High-Speed Serial Interface Test in Production

High-Speed Serial Interface Test in Production. Assure Device Interoperability In Real-World Environments. About GuideTech. Specializing in Precision Timing for Semiconductor Test and Scientific Lab Communities since 1988 Core Technologies Continuous Time Interval Analyzer (CTIA)

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High-Speed Serial Interface Test in Production

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  1. High-SpeedSerial Interface Testin Production Assure Device Interoperability In Real-World Environments

  2. About GuideTech • Specializing in Precision Timing for Semiconductor Test and Scientific Lab Communities since 1988 • Core Technologies • Continuous Time Interval Analyzer (CTIA) • Fast Datacom Analysis Software (DCA) • High Channel Count, Parallel Architecture Targeting production test of high-speed serial interfaces

  3. Semiconductor Test PLL & Spread Spectrum Clocks Source Synchronous Bus Embedded-Clock Serial I/O Scientific Analysis Jet Engine Rotation/Vibration Atomic Clock Drift & Particle decay GuideTech Keeps the Planet’s time! ASE test floor US Master Clock at the US Naval Observatory Sample Applications

  4. The Need for Speed • PCs move to high-speed serial buses in 20051 • 80% - 2.5Gbps PCI-Express • 100% - 1.5Gbps Serial-ATA • 20% - Gigabit Ethernet • But test quality is not yet assured! 1 Morgan Stanley – Sep 22, 2003 Semiconductor Capital Equipment Industry Research 2 pairs of differential channels @ >800Mbps 16 channels @ < 200Mbps Controller Device Controller Device

  5. 1.6G Source Synchronous Flat Panel DVI Digital Video Interface DUT 400MHz +/-150ps Digital Synchronous ATE Spread Spectrum PLL Clocks To lower EMI emissions of cell phones & consumer devices ATE Performance Gap 1.2G - 3.2G Embedded-clock Serial (e.g. XAUI, SATA, FC & PCI-Express) Performance GuideTech has been filling the gap since 2001 High Speed High Accuracy High Throughput Asynchronous test 2001 2004 Year

  6. A New Test Paradigm • Scope • Slow, Statistical Averaging • Gross test of Total Jitter & Eye • CTIA & DCA • Fast, Frequency Domain Analysis • Per-edge timing analysis

  7. CTIA Local Memory Meas #Event #Timestamps 1 E1 T1 , T2 2 E2 T3 , T4 3 E3 T5 , T6 Real-Time DSP Meas #Event #Pulse Width 1 E1 T2 – T1 2 E2 T4 – T3 3 E3 T6 – T5 PWE2 Continuous TIA Technology • Continuous Timestamps • Record edge timing & event count relative to (T0,E0) • Multiple measurement types derived from same data set • All measurement channels reference same (T0,E0) • Powerful Pulse Selection Arming • “Walk” measurements through data patterns • Skip pulses to measure specific pulses E0 E1 E2 E3 T0 T1 T2 T3 T4 T5 T6

  8. Non-Continuous TIA Drawbacks • Non-Continuous TIA based on simple Time Counter technology • Random, absolute measure of time intervals • No inherent reference to common (T0,E0) • Relies heavily on Statistical Analysis methods Time interval #1 Time Interval #2 • Requires physical Pattern Marker for highest accuracy • Pattern match adds test time to synchronize to patterns • Pattern match unreliable in presence of large jitter • Requires repeating SEARCH for one-shot measurements • PLL Lock Time

  9. CTIA Single-Shot Capability • Test PLL & Spread Spectrum Clocks in production • One-shot • Frequency • Modulation • Lock Time • Jitter • No arming • Picosecond accuracy • In milliseconds • 8 in parallel • Up to 64 channels

  10. fjitter CTIA Frequency Domain Analysis • CTIA time correlation enables plot of time interval error (TIE) Dt 0 Dt 1 Dt 2 Dt 3 Dt 4 Dt 5 Dt 6 Auto Correlation Plot Of Sinusoidal Jitter TIE Dt (ps) Time (us) FFT of the TIE plot provides the amplitude and frequency of sinusoidal jitter/modulation AMPLITUDE FREQ

  11. 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 Match 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 Match Pattern Marker PM selects the next desired pulse to measure 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 T0 T1 T2 T3 E0 E2 E5 E7 GT4000 Functional Test ofNon-deterministic Signals ATE Digital Compare Method –Requires Match Mode to position strobes Non-continuous TIA –Requires Marker to locate desired bit location Continuous TIA –Reconstructs repeating signals with ‘Virtual Marker’

  12. CTIA “Virtual Marker” • Edge isolation & reconstruction of non-deterministic bit patterns • Known Bit Pattern & UI • Selectable Bit Event Count • Correlated CTIA Timestamps (Tn,En) • More reliable than a physical pattern marker in high jitter signals • Reduces test times to milliseconds for… • Per-edge jitter analysis • Asynchronous pattern verification

  13. Serial Interface Test in Production • Many test options • High-$peed ATE • BERT • Scope • Jitter Analyzers • Few cost-effective approaches • Loopback • On-chip DFT/BIST But ‘no test’ is not an option anymore…

  14. Serial I/O Loopback Test • Benefits • Low-cost vs expensive ATE pin electronics • Addresses asynchronous issue with ATE TXdiff RXdiff • Drawbacks • Gross Functional Test only • Does not insure device interoperability in real-world system environments

  15. Near-end Far-end TXdiff RXdiff CTIA measures TX jitter in loopback path Assure Real-World Performance • BER helps insure real-world performance but is too slow for production • High-throughput jitter analysis can estimate BER in production • TX Jitter Analysis • Predicts far-end jitter degradation after TX signal is subjected to system connectors, switches and PCB traces

  16. Random Jitter • Causes of Random Jitter • Thermal noise • Transistor current fluctuation ‘shot’ noise • Flicker noise (1/f noise) • Random Jitter is a contributing factor to Bit Error Rate BER 10-6 10-8 10-10 10-12 SJ DJ Eye Width @ BER 10-12 QxRJ Q = 14.069 @ BER 10-12

  17. BER 10-12 QxRJ RJ is important for fast BER estimation • Measuring Bit Error Rate on a BERT can take hours or days • Quickly determine Total Jitter for a BER of 10-12 Jitterp-p = ( Q x RJRMS ) + DJ Q = 14.069 @ BER 10-12 • Due to the large Q multiplication factor, RJ measurements must not be contaminated by PJ and DDJ components Probability Density Functions (PDF) of jittering edge timing Gaussian RJ RJ contaminated by PJ RJ contaminated by DDJ

  18. Data-Dependent Jitter is Important • Most PHY-layer I/O failures are DDJ-related • Causes of DDJ • Bandwidth limitations in signal path • Frequency dependent • Pattern dependent • Output driver faults • Duty cycle distortion • Rise/fall times • Packaging

  19. CTIA DataCom Jitter Analysis • GuideTech DCA Provides: • Data Pattern Verification • Random Jitter (RJ) • Data-Dependent Jitter (DDJ) • Periodic Jitter (PJ) • Total Jitter (TJ) • Bit Error Rate (BER) • Eye Width Continuous TIA technology enables fast and accurate quality assurance

  20. Jitter Amplitude (UI) Remove Spread Spectrum Clock Modulation Remove other periodic jitter Remaining Noise Floor (Random RMS Jitter) 1UI 0.5UI 0.1UI 0.1MHz 10MHz 50MHz CTIA RJ Immune to PJ • CTIA continuous timestamping enables isolation of the RJ noise floor by removal of PJ frequency components in the FFT spectrum and DDJ using virtual marker • Statistical (Curve fit) methods are prone to estimation errors depending on the PDF shape PDF showing RJ contaminated by PJ & DDJ

  21. RJ Immunity to DDJ • CTIA continuous timestamps act as a ‘virtual’ marker • Isolate edges • Remove DDJ offset before performing FFT for RJ analysis 0 1 0 1 1 0 0 0 0 0 1 0 0 T0 IDEAL Edge-6 location Count DDJ offset 1P 1N 2P 2N 3P 3N

  22. P1 N1 P2 N2 P3 N3 P4 N4 P5 N5 P6 N6 Non-Continuous TIA Inherent DDJ inaccuracies of double-delta method* *Reference: Fibre Channel MJS document Section 12.2.2 & 12.2.7 CTIA vs. ‘double-delta’ method • CTIA measures edge shifts independently on each data bit • Produces highly repeatable DDJ results per-edge • Avoids inaccuracies of statistical double-delta methods* Continuous TIA

  23. 10x Throughput with PicosecondDCA Correlation to Scope • DCA correlates to Agilent 86100 within picoseconds • DCA test time is less than 1 sec vs. 10 sec on scope (K28.5)

  24. PJ – ON (RJ, DDJ, PJ, TJ) }PJ resolution }RJ precision Test PCI Express in 1 second (including pattern verify) PJ – OFF (RJ, DDJ & TJ only) DCA Fast Jitter Separation • Select DCA test time • Pattern length • PJ resolution • PJ ON/OFF • RJ precision Test Time (sec) 10s 5s 1s 250ms Pattern Length (bits) K28.5 PCIe PRBS15 640 bit 32,767 bits Compliance Pattern

  25. The Value of Jitter Test • Jitter test saves money • Test Escapes • Field Returns • RMA failure analysis • Lost Business • Yield Loss • Failing good devices • Time-to-Market Delays • Long characterization-to-production correlation time • Unprepared to debug unexpected process variation at final test

  26. CTIA Provides the Missing Pieces • Test Asynchronous signals • High Throughput “Virtual Marker” • Repeatable Jitter Analysis • 64 Single-ended / 32 Differential Introducing the GT4000 Continuous TIA Booth # 1420

  27. 2004 High-SpeedSerial Interface Testin Production Assure Device Interoperability In Real-World Environments

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