Current (recycler) timing/trigger system appears to be sufficient for TeV BPMs

1. Current (recycler) timing/trigger system appears to be sufficient for TeV BPMs - add injection event to beam sync - TSG FPGAs nearly full, but dropping MDAT decoder and 2 of 6 gates frees ~30% space - could run TSGs at 7.5MHz (instead of 53) - IP Digital I/O board can drive BLM ext dev bus and calibration

2. MVME2400 I/O Fanout IP Carrier Beam Sync Ext Trig 53 MHz Tclk Gate Gate Gate Gate Gate Gate Gate Gate Gate Gate Gate Gate Echotek Clk Gen 53 MHz IP Digital I/O IP UCD Tclk IP TSG IP TSG PMC UCD Cal ctrl/ BLM ext dev bus A/D clocks Existing (recycler) timing system

3. Need to re-layout I/O fanout board to include latest revisions - suggested additions/changes modify number of clock inputs and gate outputs A/D clock generator? 53 MHz repeater FPGA to incorporate functions currently on IP carrier (TSGs, Tclk UCD, Digital I/O, VME interface) Tclk, beam sync simulator

4. UCD Digital I/O TSG TSG I/O Fanout IP Carrier Option 1 Re-layout I/O Fanout board to current revision (no changes) [5 weeks]

5. FPGA FPGA I/O Fanout I/O Fanout Option 2 Re-layout I/O Fanout board with on-board or mezzanine FPGA [6-7 weeks]

6. UCD FPGA Digital I/O TSG TSG Fanout IP Carrier Use existing IP version until firmware is ported to new FPGA

7. Cal Filter BPM RF Relay Echotek Cal Filters BPM RF Relays Echotek Calibration select (optional filter select)

8. Cal Filters A A B B Calibration signal applied to any one of four BPM ports can be monitored on other three ports.

9. RF relays Filters MAX4820 Calibration Board [4-5 weeks]

10. Digital Receivers (BLM) CPU Timing Echotek Clock Gen PMC UCD Calibration Splitters

11. Digital Receivers (BLM) CPU Timing PMC UCD (Clock generator incorporated in Timing board) Calibration