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ECE 353 Introduction to Microprocessor Systems. Michael J. Schulte. Week 10. Topics. System Timing Hardware/software trade-offs Execution time Bus Timing Wait states Memory device timing parameters Timing compatibility Time Measurement Delay loops Hardware timers. System Timing.
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ECE 353Introduction to Microprocessor Systems Michael J. Schulte Week 10
Topics • System Timing • Hardware/software trade-offs • Execution time • Bus Timing • Wait states • Memory device timing parameters • Timing compatibility • Time Measurement • Delay loops • Hardware timers
System Timing • Hardware/software trade-offs • Task allocation • Real-time systems • Soft real-time versus hard real-time • Microprocessor clock frequency • Execution time • Affected by numerous variables • Difficult to predict • Sample Instructions • Delay loops
WAIT States • WAIT states are used to lengthen the bus cycle for slower devices • Extra T3 states are run • WAIT state control • CSU WS setting • READY signal • Normally ready • Normally not-ready • External circuits • CSU RDY setting
Memory Device Timing • Read Cycle • TAA / TOH • TACS / TCHZ • TOE / TOHZ • TRC • Effect of grounding device’s /CS • Write Cycle • /WE vs. /CS controlled • Timing Parameters • Write cycle
80C188EB Timing Compatibility • Need to determine if devices are compatible with the microprocessor at the selected clock speed. • Want to ensure that all system timing constraints are met at minimal cost. • Two basic timing issues to resolve: • Setup and Hold Times • Latching information (inputs) • Output Delay and Float Times • State changes (propagation delays) • Turning drivers on and off (outputs)
Assessing Timing Compatibility • Need to know whether CPU will operate with the TAA for given device. (read cycle) • Address becomes valid at start of T1 • Data is latched by CPU at start of T4 • To get an accurate TAVDV, must include the delays for the address becoming valid, and include the setup time for data. • Address valid delay relative to CLKOUT edge • Setup time required relative to CLKOUT edge • A.C. Specifications 1 & 2
System Timing Compatibility • Need to account for all delays in a system to assess timing compatibility. • Consider the system in Fig 13.5-2. • Analyze the read timing with regard to: • TACC – address access time • TCE – chip enable to valid data • TOE – output enable to valid data • TDF – output hold time • How do wait states impact the timing? Read Cycle A.C. Specs 1 , 2Relative timings
System Timing Compatibility • Consider again the system in Fig 13.5-2. • Analyzing write cycle timing. • TW, TDW, TDH • TASW, TAW, TCW • TWR • Device characteristics are just a part of timing • Line/device capacitance and driver slew rates • Transmission line effects • Impedance mismatch and reflections • Skew and trace length mismatch • Signal integrity Read Cycle A.C. Specs 1 , 2Relative timings
80C188EB Timer/Counter Unit • Timer/counter modules used to • Generate signals with specified frequency / duty cycle • Count external events, measure pulses • Generate absolute delays, periodic interrupts • Three independent timer/counters • Timer 0/1 • Modes of operation • Continuous / Non-continuous • Single or Dual Maximum Count • Input Sources • Flowchart • Configured and operated through PCB registers • T0CON, T0CNT, T0CMPA, T0CMPB
80C188EB Timer/Counter Unit • Timers 2 is much more limited. • Operated through PCB registers • T2CON, T2CNT, T2CMPA • Useful as a prescaler or as a periodic interrupt source. • Timer applications • Frequency measurement. • Waveform generation.
82C54 PIT/C • Provides additional timer/counter resources for microprocessor system. • Appears as 4 byte-wide registers • Control register (3) • Timer registers (0,1,2) • Program by writing 3 bytes in sequence • Control byte • Timer word • Three independent 16-bit counters • BCD or binary • DC-10MHz input range • Multiple modes of operation
Real-Time Clocks (RTCs) • RTCs provide microprocessor systems with absolute time information • Absolute time does not necessarily mean calendar/clock time • Typically operate from 32.768KHz crystal with battery or capacitor back-up power supply • Generate periodic interrupts • Often contain small amount of RAM – historically this was where the PC stored its configuration (BIOS) settings since it is non-volatile. • Dallas Semiconductor DS1375
Watchdog Timers • Watchdog timers are used to guard a system against lock-up due to software errors or soft failures in hardware. • Often included in CPU supervisor circuits. • Retriggering usually done in the main program loop. • Watchdog output can be used to reset the CPU or as a nonmaskable interrupt (NMI). • Maxim MAX6323/MAX6324
