Improving Soft-error Tolerance of FPGA Configuration Bits

1. Improving Soft-error Tolerance of FPGA Configuration Bits Suresh Srinivasan, Aman Gayasen, N. Vijaykrishnan, M. Kandemir, Y. Xie, M.J. Irwin

2. Introduction • SRAM-based FPGA are increasing • Soft errors because of • Cosmic radiation • Radiations emanating from materials used in process • Upsetting the data value stored

3. Introduction • Asymmetric SRAM (ASRAM) structure • Soft error immunity and low leakage • Based on an observation • 87% configuration stream bits are zero

4. FPGA architecture • Island-style SRAM-based FPGAs • SRAMs in two purposes • Routing multiplexers • Look Up Tables (LUTs) • Flip in the SRAM cell  Soft errors

5. FPGA architecture-Observation • The ones and zeros in SRAM are uneven. • The critical configuration bits is less than 40% of all • A majority of critical bits are zeros. (75%) • 90% were the bits for routing muxes • ASRAM-0 • Reduce leakage • Reduce susceptibility to soft errors • But only 42% of LUT bits are zeros – maximize zeros

6. Asymmetric SRAM off 1 off 0 vdd

7. Asymmetric SRAM

8. Asymmetric SRAM FIT = failure in 109 hours of operation

9. Maximize zero methodology

10. Maximize zero methodology

11. Experiment results

12. Experiment results

13. Conclusion • Exploit the large number of zeros • Increase the immunity to soft errors • Use asymmetric SRAM to reduce FIT