A 1.6 Gbps, 3 mW CMOS Receiver for Optical Communication

1. A 1.6 Gbps, 3 mW CMOS Receiver for Optical Communication Azita Emami-Neyestanak, Dean Liu, Gordon Keeler, Noah Helman and Mark Horowitz

2. Optical Interconnect Systems • Optical to electrical conversion • Reshaping/retiming • Data recovery • Photo-diodes are used for conversion • Modeled as a single-ended current source & its Parasitic capacitor • Long-haul vs. short-haul A. Emami and M. Horowitz

3. Receivers for Long-haul Links • Design goals • High sensitivity • High gain, low input noise current • Large bandwidth • Issues & trade-offs • Power dissipation • Area • Cost A. Emami and M. Horowitz

4. Transimpedance Amp • Good sensitivity • Low input impedance • Needs high GxBW • Post amplification • Power & area Rf Iop A A2 Cp A. Emami and M. Horowitz

5. Receivers for VLSI Photonics Vdet • Short-haul parallel links • Dense arrays of receivers • Low power, area • High bit rate • Cheap standard process • Diode clamp front end • Simple, low power, area • Needs differential input • Low sensitivity V1 V2 -Vdet A. Emami and M. Horowitz

6. Outline • Introduction • Double Sampling Integrating Receiver • Implementation • Measurement Results • Conclusions A. Emami and M. Horowitz

7. IDC=(I0+I1)/2 1 1 0 1 t0 t1 t2 time d0 d1 d2 Integrating Front-End Vdd di di=0aIop= I0 di=1aIop= I1 Iop Cp Vin A. Emami and M. Horowitz

8. Vin(t2) < Vin(t1)ad2= 0 Vin(t1) Vin(t0) Vin(t2) IDC=(I0+I1)/2 Double Sampling, Data Resolution Vdd Vin(t1) > Vin(t0)ad1= 1 di Vin(t) 1 1 0 1 t0 t1 t2 time d0 d1 d2 A. Emami and M. Horowitz

9. Double-Sampling Integrating RX • Integrates the optically generated current onto the parasitic input capacitor • Samples the voltage of the input node at two consecutive bit times • Compares these two voltages to decide the signal value A. Emami and M. Horowitz

10. Vin(t1) d1 Vin(t2) Vin(t0) Vin(t0) d2 Vin(t2) Vin(t1) Vin(t1) Receiver’s Block Diagram Vdd + f1 Sense Amp - Vin C1 Photodiode Clk_1 f2 Offset + C2 Sense Amp - IDC Low-Pass Filter Clk_2 Double-Sampler Offset A. Emami and M. Horowitz

11. Circuit Issues • Double sampling • Charge injection • Charge sharing • High resolution comparator design • Need accurate offset compensation • Comparator kick-back (each sample is used twice) • Generating IDC A. Emami and M. Horowitz

12. Double Sampling • Duty-cycles < 50% for f1 and f2 • Clk_1,2 triggered after equalized charge coupling f1 f2 t0 t2 f2 Clk_1 f1 t1 Clk_1 Clk_2 Clk_2 A. Emami and M. Horowitz

13. Clocked Sense Amplifier Vdd Clk Clk Clk OutP OutM A B 1mm 1mm 4mm 4mm InP InM x4 x4 x2 x8 x2 x8 [6] [0] [5] Offset[3] Offset[4] [7] [2] [1] • Offset compensated, 6mV resolution, +100mV range • Voltage controlled PMOS capacitors [Lee, et al., JSSC Nov’00] • Sizing trade-offs: power, area, speed and mismatches Clk A. Emami and M. Horowitz

14. Clk_1 Eval. VB1 f1 B1 A1 Vin InP InM • When B1 is discharged, A2 is charged • Total zero kick-back Clk_2 VA2 A2 B2 InP InM Reset Kick-Back • Similar waveforms at A1 and B1 A. Emami and M. Horowitz

15. Input Node Control • IDC=(I0+I1)/2 • DC-balanced data • Negative feedback • LPF(Vin) controls IDC • Sets DC value of Vin Din Vdd Vin IDC 1 1 0 1 Low-Pass Filter A. Emami and M. Horowitz

16. Generating IDC • Filter-out DVin • Set IDC by DC level of Vin VBias Cz VSet Vin IDC Clk_b Clk VBias Cz Switched Cap RC network with added zero R C A. Emami and M. Horowitz

17. PD/CP/Bias L2H L2H Input Clock FSM Timing • CMOS buffer-based dual-loop DLL [Wei, et al., JSSC Nov ’00] A. Emami and M. Horowitz

18. CMOS Test Chip, GaAlAs Detectors After the flip-chip bonding A. Emami and M. Horowitz

19. Optical Testing A. Emami and M. Horowitz

20. Input Capacitance Measurement • Send n “1”s, followed by n “0”s • On-chip analog measurement of input node voltage, DVin • Measure the replica of IDC , when I0=0 • Cin= n x IDC / ((bit-rate) x DV) • Cin= 420 fF A. Emami and M. Horowitz

21. Input Node Waveform Recovered Data Vin A. Emami and M. Horowitz

22. Receiver Sensitivity • Minimum detectable optical power • Long sequences of “0”s and “1”s stress the receiver the most • Limited voltage headroom • Time variations of IDC A. Emami and M. Horowitz

23. Receiver Sensitivity • Unbalanced input data shifts IDC • Can be used to measure the sensitivity • Smaller voltage swing in one direction I1 IDC I0 A. Emami and M. Horowitz

24. Receiver Sensitivity • 1.6Gbps, DC-balanced data • 420fF input cap aI1-I0=11mA aDVin= 8 mV aP = 22mW (0.5A/W diode responsivity) A. Emami and M. Horowitz

25. Dynamic Range • DC-balanced over N bits • In low power regime, N could be large • In high power regime, headroom constrains N • Leak out the extra current in high power regime A. Emami and M. Horowitz

26. Receiver’s Performance • Supply voltage 2.5v • Technology National 0.25 mm CMOS • Input data rate 1.6 Gbps • Photodetector capacitance 270fF • Total input capacitance 420fF • Sensitivity (input photo current) 11mA • Power dissipation 3mW • Area 80mm × 50mm A. Emami and M. Horowitz

27. Conclusion • The Integrating, TIA-less receiver: • Very low power & area • Good sensitivity & bandwidth • Has some clocking constraints • Needs accurate offset compensation • Suitable for very dense arrays of optical receivers on chip A. Emami and M. Horowitz