Particles and Fields Package (PFP) Instrument Preliminary Design Review June 15, 2010

1. Particles and Fields Package (PFP) Instrument Preliminary Design Review June 15, 2010 Dorothy Gordon

2. PFDPU Agenda

3. Requirement Sources Mission Requirements MAVEN_PF_QA_002, PFP Mission Assurance Implementation Plan MAVEN-PM-RQMT-0005D_MRD.xlsx MAVEN-PFIS-RQMT-0016B.xls Particle and Fields Functional Requirements Document (FRD) Environmental Requirements Document MAVEN-SYS-RQMT-0010 Interface Control Documents MAVEN_PF_SYS_004B_PFDPUtoInstrumentICD.doc PFDPU to Instrument Interface Control Document ICD MAVEN-SC-ICD-0007 Spacecraft to PFDPU Interface Control Document

4. PFDPU Driving Requirements (1)

5. PFDPU Driving Requirements (2)

6. Functional Block Diagram PFDPU Components and External I/Fs

7. Electrical Block Diagram

8. Particles and Fields Package (PFP) Instrument Preliminary Design Review PFDPU Particles and Fields Data Processing Unit Mechanical Packaging Design Bill Donakowski (Paul Turin) UCB/SSL

9. PFDPU Design Description Design based on UCB/SSL Heritage Designs Machined Al Alloy Box Frames for each Card Box Assy consists of 11 individual cards (each card is complete box) Frames have interlocking features at interface to adjacent frame Frames bolted together via threaded skewers S/C Attach Frame at bottom Bolted to each Box Frame Bolted to S/C Panel 9.3” 8.0” 7.0” S/C Attach Frame (bolted to each Card Frame) Individual Card Frames

10. PFDPU Assembly Details 2X Threaded Rod Skewers PC/104 Connector Individual Box Cards (6061 T6 Al) S/C Attach Frame (6061 T6) End Shields (6061 T6 Al) 6 X Attach Feet to S/C Attach Bolts to Box Frames

11. PFDPU Cards Stacking 11 Cards: Reg 1, DCB 1, Reg 1, DCB 2, IIB, Sep 1, Sep 2, Mag 1, Mag 2, LPW DFB, LPW BEB 2 Different Card Widths, .700” and 1.15”

12. PFDPU Interlocking Frame Overview EMI Shield (.031” thick) PCB (.0625” thick) Frame (.100” thick) Interlocking Features

13. PFDPU Typical Card Layer D-Connector (to S/C or Instrument) Attach Screws Nuts PCB PC104 Interconnect EMI Shield (PCB FR4/Cu) 6061 T6 Aluminum Box Frame

14. PFDPU Typical Card Layer

15. PFDPU INTERFACE to S/C Bolted to S/C Panel Thermally coupled to S/C Electrically grounded to S/C Via Ground Straps Straps provided by L-M

16. PFDPU Drawing Status Released Maven PFDPU Board Outline Distributed to Electrical Designers for Board Layouts (March 2010) • Released Preliminary MICD • Sent to L-M (April 2010)

17. PEER Review Items All PEER Review Requests will be incorporated into design

18. PFDPU Potential Design Changes Accommodate electrical design layouts Electrical layouts ongoing Connector locations and type Frame Cross Sections Section properties may be increased If required for greater strength or stiffness

19. Particles and Fields Package (PFP) Power June 15, 2010 Peter Berg

20. Power System ERD MAVEN-PF-SYS-004B PFIDPU ICD MAVEN_PF_SYS_003 Power Converter Requirements ICD MAVEN-SC-ICD-0007 Requirements Sources

21. Power System – Overall Block Diagram

22. Power System REG BOARD (one of a redundant pair) Main 28 Volt Isolated converter DCB converter Distribution Switches Actuator Switches Monitors

23. Power System – REG Board

24. Power System - INSTRUMENT INTERFACE BOARD Instrumentpowerconverters • MAG (X2) • MAG Heater (X2) • SEP • LPW

25. Power System – IIB Board

26. Typical Outboard Low Voltage Converter

27. Power System – RFA Response

28. MAVEN PFDPU DCB (Board and FPGA) June 15, 2010 D. Gordon

29. DCB in the PFDPU

30. DCB Block Diagram

31. DCB Basic Subsystems • Design Document • PFDPU Data Controller Board Specification, Rev E. • Data Controller Board and FPGA Description and “User Manual” • Basic Subsystems • C&DH Interface • Commands arrive via UART (57.6Kbaud) • Telemetry transmitted via UART (57.6Kbaud) • Discrete Commands arrive via Optocoupler Interface • S/C RESET, SC CLK1HZ, SIDESELECT • Memory • Boot ROM, EEPROM, CPU SRAM and Instrument SRAM • FLASH – 8Gbytes in two separately powered 4Gbyte modules • Instrument Interface - Mode Setup and Data Ingest • Instrument initialization parameters as outlined in ICDs

32. DCB Basic Subsystems (continued) Basic subsystems (continued) Timekeeping Internal 16.78 MHz (224 Hz) system Provides instrument timebase (Sample Time) Logic timestamps S/C CLK1Hz with respect to Sample Time Generates CPU Interrupts and Watchdog Timer Reset Provides Instrument DMA Buffer Swap “ticks” Housekeeping REG forwards analog signal to DCB based ADC (1604) DCB based housekeeping channels via 8-channel mux FSW controls analog mux address FSW samples data at regular intervals

33. DCB FPGA DCB – Data Controller Board DCB FPGA is the RTAX2000S-1CG624E Advanced testing phase: AX2000-1CG624 (same footprint – fused device) Initial Development phase: A3PE3000-FG324 (FLASH device) via the “FPGA Daughter Board” 10K R-Cells, 21K C-Cells, 36Kbytes Internal SRAM System Clock = 16.78MHz – independent onboard oscillator Estimated Power: 250mW at 25C 650mW at 75C Utilization Estimate ~75% modules; 190 I/Os (constrained by FPGA daughter card to ~200 max) Block RAM: 4 blocks for S/C CMD IF memory and 1 block for InstCmdFIFO (out of 64 block total) (error correction will increase utilization)

34. DCB FPGA Subsystems Coldfire V1 CPU Core 32-bit microprocessor core with 24-bit address bus IP Core, delivered in January, supported by IPExtreme CPU Bus Interface AMBA 2 AHB Unified instruction/data bus decoded by FPGA Interfaces with internal Register bank and MBUS for external memory and peripherals Registers I/O Bank and Actuator Control MBUS Control Spacecraft Interface Commands via Dual Port Memory Telemetry via DMA (8 channels)

35. DCB FPGA Subsystems (continued) Instrument CDI Commands via FIFO 256 Word Instrument FIFO provides 6.8 ms of buffer (one FIFO shared between the 7 instruments) Message Intake via DMA Each Instrument allocated its own double-buffered segment within SRAM Buffers are configured to swap either every second, every 2 seconds or every 4 seconds (synchronous to the instrument acquisition cycles) Timekeeping Sample Time available to FSW via the Register I/F Timestamped S/C 1Hz via the Register I/F F0 Command generated and forwarded to Instruments via CDI Interface

36. DCB FPGA Subsystems (continued) REG (LVPS) Interface Instrument Power Switches Overcurrent control handled by the logic Inrush guardband when switch is activated (10ms to 100ms) Override possible via Command I/F Overcurrent status from LVPS per instrument Switch is turned off if the Inrush Guardband and the Override are both deasserted when the Overcurrent signal is asserted Actuator Control (Switches reside on the REGs board) Time of activation is settable via Register Interface Two pulse duration controls EUV Door: ¼ second increments up to 16 seconds SEP, SWIA and STATIC switches: 1/32 second increments up to 2 seconds Addressed actuator must be armed and fired SEP, SWIA, STATIC digital status is available via optocoupled feedback EUV Door status available via LPW Housekeeping

37. DCB FPGA Subsystems (continued) FLASH Memory Control Addresses two stacked memory modules (3D-Plus Module, Samsung die: 3DFN32G08VS8289) Each module is 2G x 8, using eight 256M x 8 FLASH components Each 3D-Plus FLASH Module is independently isolated -- switchable power Defaults to off at power on; turns off with watchdog reset Devices are kept off during periods of inactivity Optimize TID lifetime and minimize power drain Reset command issued at the beginning of each DMA Transfer Minimizes impact of Single Event Functional Interrupts (SEFI) Error correction option – Hamming code Correction applied to 512 byte segments for DMA writes Error detection/correction during readout DMA mode: transfers data to/from SRAM CPU sets up DMA; handles buffer allocation and bad block management Processor mode: CPU can read/write as a device in memory mapped mode Bad blocks tracked by ground software

38. DCB Board Schematics are in process FPGA Daughter card details are being worked through Board layout scheduled for June, July 2010 Current Estimates:

39. Initial Placement

40. Long Leadtime Parts

41. Peer Review Action Items Peer Review for MAVEN Digital/FPGA Designs held on May 12, 2010 28 Recommendations and 4 Action Items All have been responded to and closed (responses are posted on the ftp site) Most recommendations are suggestions resulting from the schematic walkthroughs RFAs related to CGA and FPGA Daughter card affect both DCB and STATIC FPGAs

42. Peer Review Item 29 (Action) Two processors on simultaneously Action Request: Complete analysis of impact of having two processors on at the same time. Response: The intended operation would power only one side of the S/C at any one time. Powering both sides is an operator error. However, operator errors do occur, so the design must assure that no subsystem would be compromised or damaged if both sides of the S/C are on simultaneously. At the signal level, a "Cold-Spare" interface, protected via series resistors, insures that these DCB output buffers are protected. The question asked was: what occurs on the interface if both processors start sending commands to the instruments. Should this occur, there are numerous safeguards that prevent damage: 1. There is not an issue with the actuators unless both operational and actuator power services are on for both sides (less likely case) 2. Spacecraft agrees to add software to ensure that both power services are not on at the same time. We will verify that this appears in the next revision of the ICD. 3. Even if both are on at the same time for a short time (until the Spacecraft software recognizes the problem and fixes it) the instrument is prevented from running actuators for a few minutes after power on (part of the exisiting design to preclude having the safing system contend with the operational system). 4. After power-on the instruments are off and will remain off till commanded on, so no instrument commands will be sent. 5. All instrument commands are error checked and only executed in the event that there are no framing or parity errors. Ongoing: Power Feeds are cold-spared (as described earlier during the LVPS presentation) in addition to the Instrument signal I/Fs. We will continue to pay attention to this aspect of the system as design and testing progresses.

43. Schedule (1)

44. Schedule (2) • Upcoming tasks: • DCB schematic completion and PCB Layout (June - July) • DCB FPGA Design and Simulation (July - August) • DCB EM Test Debug (September – October)

45. Particles and Fields Package (PFP) Instrument Preliminary Design Review FPGA Design/Development June 15, 2010 D. Gordon

46. FPGA Design Framework Synchronous Top Level Clock HCLK 16.8MHz for DCB, 8.4MHz for SEP, 1.0MHz for SWEA/SWIA 24MHz for STATIC Derived Clocks from DCB forwarded to instruments and LVPS Small State Machines Failure-Tolerant Operation by top level design Unit Testing is Contained Gray Coded Undefined States return to IDLE Resets HW_Reset_In is Conditioned as per Guidelines FPGA Global Reset = Conditioned Reset ORed with Watchdog Reset and S/C Reset for most DCB FPGA Modules ORed with Commandable Reset for most Instrument FPGA Modules

47. FPGA Parts and Prototyping Two Type of FPGAs used for MAVEN RTSX72SU-CQ208 for SWEA, SWIA and SEP Footprint compatible Protoboard Part: A54SX72A-PQ208 Flexibility exists to verify either part on the proto and/or flight board Use A54SX part with socket until design is fully checked out RTAX2000-1CG624 for STATIC and DCB Use A3PE3000-FG324 as Protoboard Part during development Two types of Daughter cards (for CG624 and FG324) Use of Daughter Card allows for footprint compatibility between Flight and Protoboards Can verify either part on the proto and/or flight board The AX2000-1CG624 is footprint compatible with the RTAX2000-1CG624 option for an interim test-step before programming the flight part

48. FPGA Development Process • All Module and Top Level code is tested/exercised • Stress testing (much of which is not possible at top level) is performed at module level (e.g. full “stackup” of requests to Memory Controller/Arbiter). State machines are taken through all branches. • Each module is functionally verified (testbench, tcl script). When feasible, data is written out in text format to ease regression testing. • Simulation/testbench framework established during Proto/ETU Phase. • Top level functional simulations write out log files (MBUS Traces, Telemetry and FLASH Logs). The text files saved and facilitate regression testing. Functional simulation results are compared to timing simulation results

49. Configuration Management Each FPGA Revision is numbered Revision log maintained, lists reasons and details for all deltas from previous version Revision Number is embedded in the FPGA Directory frozen/saved for each FPGA revision Source code, synthesis, stimulation, simulation, P&R can be retrieved for any revision Description and Module level history included in header to each HDL File Flight FPGA uses HDL identical to the Proto FPGA HDL linked to a common directory Minor differences due to architectural differences (i.e. memory instantiation)

50. Backup Slides