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Earth Atmosphere Solar-Occultation Imager (EASI)

Earth Atmosphere Solar-Occultation Imager (EASI). Electrical Design Estimates C. Paul Earle 2 August 2002. Functional Block Diagram. Mechanism Control Box. +28V Survival Power. Actuators. Telescope. Main Electronics (warm). Readout Electronics. H/K. 2 InSb Arrays (1Kx1K). Science.

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Earth Atmosphere Solar-Occultation Imager (EASI)

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  1. Earth AtmosphereSolar-Occultation Imager(EASI) Electrical Design Estimates C. Paul Earle 2 August 2002

  2. Functional Block Diagram Mechanism Control Box +28V Survival Power Actuators Telescope Main Electronics (warm) Readout Electronics H/K 2 InSb Arrays (1Kx1K) Science Timing (1pps) RISC Processor (RAD6000) & Memory Readout Electronics Storage/ Downlink Science Data I/F 5 Si Arrays (128x128) Centroiding Readout Electronics S/C C&DH 1553 I/F Si Array (128x128) Fringe Sensing DC/DC Converter USES Data Compression Thermal Control +28V Supply Cryo-Cooler +28V Supply Figure 1.

  3. Design Assumptions • Two (2) InSb (1K x 1K) Array For Science • - 10mSec Integration, 90mSec Readout, 18 bits/pix • - Full Frame Readout Mode (Diagnostic) • - Science Readout Mode (~10% Focal Plane) • Five (5) Si (128 x 128) Array for Centroiding • One (1) Si (128 x 128) Array for Fringe Sensing

  4. Science Data Rate • Assumptions: 10mSec Integration, 90mSec Readout, and 18bits/pix • FPA Readout Rate ~ 2(1Mpix)x(18 bits/pix)/(90mSec) ~ 400Mbps (avg) Current Downlink (D/L) Capability from L-2: ~ 20Mbps • 1 Frame every 1.8 Sec (ie. 36Mpix/20Mbps) - (meets science requirements) Full-Frame Mode (Diagnostic): - Readout 1 Frame every 1.8 Sec (vs. 10 Frames/Sec), - Onboard Data Compression (at least 2:1), Consider Utilizing GSFC’s Programmable Compression Chip (USES) - Consider adding Memory Board and limit Readout (say n Seconds) Science Mode (Onboard Processing): - Readout 10 % (or less) of Focal Plane < 40Mbps - Compute Average of 10 Frames < 4Mbps (meets D/L constraints)

  5. Circuit Board Functional Allocation Main Electronics Box • 1 Processor & H/K Board • 2 Main FPE Control Boards • 2 Main FPE Analog Boards • 1 CCD Readout Board (Centroiding & Fringe Sensing) • 1 Thermal Control Board • 1 Power Board

  6. Main Electronics Box Summary Main Electronics Box 2 Power (@ 20W) 1 Thermal Control (4W) 1 CCD Readout (4W) 2 FPE Analog (@ 4W) 9 in 2 FPE Control (@ 3W) 1 Processor& H/K (4W) 8 in 15 in 12 in 10 in Estimated Mass ~ 7 Kg Estimated Power ~ 66 Watts (Avg.) Estimated Size ~ (9 x 10 x 15) in. Figure 2.

  7. Power Requirement Summary Spacecraft Power Bus Requirement * 70 Watts + 30 Watts for conditioning

  8. Conclusion • No Electrical Design Issues or Concerns at the Instrument level. • Potential Power Subsystem Challenges Exist For Solar Array • Sizing At The Observatory Level Due To Solar Occultation In • L2 Orbit. • Focal Plane Readout Electronics Estimates Extrapolated From • As-Built IRAC Design. • Development cost ~ $4M- $5M (IRAC actuals). Includes • Design, Fabrication, & Test of one Flight Unit and one • Engineering Unit.

  9. Backup Slides (Electrical Design Estimates)

  10. Processor & H/K Board Startup ROM 1553 I/F CPU RAD 6000 1553 I/F RAM (Data Processing) EEPROM Memory (Data Processing) Time Stamp Function S/C 1pps S/W Dev. Ethernet I/F Compression Chip (USES) Housekeeping MUX & A/D RAM - UTMC (1Gbits Stack) Figure 3.

  11. FPE Analog Board Pre-Amp 18 18 Detector Output FPE Data A/D Latches DSP I/F convert latch Pre-Amp 18 18 Detector Output FPE Data A/D Latches DSP I/F convert latch Pre-Amp 18 18 Detector Output FPE Data A/D Latches DSP I/F convert latch Pre-Amp 18 18 Detector Output FPE Data A/D Latches DSP I/F convert latch (1 of 2 boards shown) Figure 4.

  12. FPE Control Board convert Array Clocks Level Shifters Array Row, Col latch State Machine (ACTEL) DC Biases Processor I/F Array Biases Address Analog MUX Data Analog Monitor (1 of 2 boards shown) Figure 5.

  13. - - + + + + - - - - + + From Processor I+ I+ Thermal Control Board DAC From Processor V+ Heater Tsensor HK Mux Heater Current Heater Voltage + To Central HK - Tsensor Voltage Tsensor Current VRef ISource (1 of n circuits shown) Figure 6.

  14. Main Electronics Power Board I+ DC/DC Converter (70% eff.) +28 VDC +15 V I+ +5 V Current Sense + - Voltage Sense + - Figure 7.

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