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Datapaths

Datapaths. Discussion D8.2 Example 37. Integer Square Root. unsigned long sqrt(unsigned long a){ unsigned long square = 1; unsigned long delta = 3; while(square <= a){ square += delta; delta += 2; } return (delta/2 - 1); }. Integer Square Root.

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Datapaths

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  1. Datapaths Discussion D8.2 Example 37

  2. Integer Square Root unsigned long sqrt(unsigned long a){ unsigned long square = 1; unsigned long delta = 3; while(square <= a){ square += delta; delta += 2; } return (delta/2 - 1); }

  3. Integer Square Root unsigned long sqrt(unsigned long a){ unsigned long square = 1; unsigned long delta = 3; while(square <= a){ square += delta; delta += 2; } return (delta/2 - 1); }

  4. Integer Square Root

  5. Datapath unsigned long sqrt(unsigned long a){ unsigned long square = 1; unsigned long delta = 3; while(square <= a){ square += delta; delta += 2; } return (delta/2 - 1); } • The following steps can be used to create a datapath for implementing an algorithm. • Draw a register (rectangular box with input at the top and output at the bottom) for each variable in the algorithm. For the algorithm in Listing 1 these would include a, square, delta, and outreg (for the return value). Each register will also have a reset, clock, and load inputs. When the reset signal is high, the output of the register will be a predetermined initial value. If the load signal is high, then on the next rising edge of the clock signal the input value will be loaded into the register and appear on the output. • Define combinational blocks to implement any necessary arithmetic or logical operation. • Connect the outputs of the registers to the inputs of the appropriate arithmetic and logical operations, and connect the outputs of the arithmetic and logical operations to the appropriate registers. Multiplexers can be used if the input to a register can come from more than one source.

  6. unsigned long sqrt(unsigned long a){ unsigned long square = 1; unsigned long delta = 3; while(square <= a){ square += delta; delta += 2; } return (delta/2 - 1); }

  7. A Generic Register with an initial value of 0 - 3 entity regr is generic(N: integer; bit0: std_logic; bit1: std_logic); port ( d: in STD_LOGIC_VECTOR (N-1 downto 0); load: in STD_LOGIC; reset: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (N-1 downto 0) ); end regr;

  8. A Generic Register with an initial value of 0 - 3 architecture regr_arch of regr is begin process(clk, reset) begin if reset = '1' then q <= (others => '0'); q(0) <= bit0; q(1) <= bit1; elsif (clk'event and clk = '1') then if load = '1' then q <= d; end if; end if; end process; end regr_arch;

  9. -- Example 37: Square root datapath library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity SQRTpath is port ( clk : in std_logic; reset : in std_logic; ald : in std_logic; sqld : in std_logic; dld : in std_logic; outld : in std_logic; sw : in std_logic_vector(7 downto 0); lteflg : out std_logic; root : out std_logic_vector(3 downto 0); square : out std_logic_vector(7 downto 0); delta : out std_logic_vector(4 downto 0)); end SQRTpath;

  10. architecture SQRTpath of SQRTpath is component regr generic(N: positive; bit0: std_logic; bit1: std_logic); port ( d: in STD_LOGIC_VECTOR (N-1 downto 0); load: in STD_LOGIC; reset: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (N-1 downto 0) ); end component;

  11. signal a: STD_LOGIC_VECTOR (7 downto 0); signal sq, s: STD_LOGIC_VECTOR (8 downto 0); signal del, del2: STD_LOGIC_VECTOR (4 downto 0); signal outin: STD_LOGIC_VECTOR (3 downto 0); constant bus_width9: integer := 9; constant bus_width8: integer := 8; constant bus_width5: integer := 5; constant bus_width4: integer := 4; begin

  12. adder8: process(sq, del) begin s <= sq + ("000" & del); end process; plus2: process(del) begin del2 <= del + 2; end process;

  13. minus1: process(del) begin outin <= del(4 downto 1) - 1; end process; lte: process(sq, a) begin if(sq <= ('0' & a)) then lteflg <= '1'; else lteflg <= '0'; end if; end process;

  14. aReg: regr generic map(N => bus_width8, bit0 => '0', bit1 => '0') port map(d => sw, load =>ald, reset => reset, clk =>clk, q => a); sqReg: regr generic map(N => bus_width9, bit0 => '1', bit1 => '0') port map(d => s, load => sqld, reset => reset, clk =>clk, q => sq);

  15. delReg: regr generic map(N => bus_width5, bit0 => '1', bit1 => '1') port map(d => del2, load => dld, reset => reset, clk =>clk, q => del); outReg: regr generic map(N => bus_width4, bit0 => '0', bit1 => '0') port map(d => outin, load => outld, reset => reset, clk =>clk, q => root); square <= sq(7 downt0 0); delta <= del; end SQRTpath;

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