ELEC 7770 Advanced VLSI Design Spring 2010 Power and Ground

1. ELEC 7770Advanced VLSI DesignSpring 2010Power and Ground Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10 ELEC 7770: Advanced VLSI Design (Agrawal)

2. References Q. K. Zhu, Power Distribution Network Design for VLSI, Hoboken, New Jersey: Wiley, 2004. M. Popovich, A. Mezhiba and E. G. Friedman, Power Distribution Networks with On-Chip Decoupling Capacitors, Springer, 2008. C.-K. Koh, J. Jain and S. F. Cauley, “Synthesis of Clock and Power/Ground Network,” Chapter 13, L.-T. Wang, Y.-W. Chang and K.-T. Cheng (Editors), Electronic Design Automation, Morgan-Kaufmann, 2009. pp. 751-850. J. Fu, Z. Luo, X. Hong, Y. Cai, S. X.-D. Tan, Z. Pan, “VLSI On-Chip Power/Ground Network Optimization Considering Decap Leakage Currents,” Proc. ASP-DAC, pp. 735-738, 2005. Decoupling Capacitors, http://www.vlsichipdesign.com/index.php/Chip-Design-Articles/decoupling-capacitors.html ELEC 7770: Advanced VLSI Design (Agrawal)

3. Supply Voltage 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Supply voltage (V) 0.25 0.18 0.13 0.1 Minimum feature size (μm) ELEC 7770: Advanced VLSI Design (Agrawal)

4. Gate Oxide Thickness 60 50 40 30 20 10 0 Gate oxide thickness (A) High gate leakage 0.25 0.18 0.13 0.1 Minimum feature size (μm) ELEC 7770: Advanced VLSI Design (Agrawal)

5. Power Supply V(t) Rg + – R C R C VDD Gate 2 Gate 1 ELEC 7770: Advanced VLSI Design (Agrawal)

6. Switching Transients VDD VDD Rg/(R+Rg) V(t) 0 time, t Only Gate 1 switches (turns on): V(t) = VDD – Rg VDD exp[– t/{C(R+Rg)}]/(R+Rg) ELEC 7770: Advanced VLSI Design (Agrawal)

7. Multiple Gates Switching VDD 1 2 3 Gate output voltage Number of gates switching many 0 time, t ELEC 7770: Advanced VLSI Design (Agrawal)

8. Decoupling Capacitor i(t) VL(t) t=0 a Rg VDD = 1 t=0 t + – Rd Cd IL A capacitor to isolate two electrical circuits. Illustration: An approximate model: ELEC 7770: Advanced VLSI Design (Agrawal)

9. Approximate Load Current, IL 0, t < 0 at, t < tp IL = a(2tp – t), t < 2tp 0, t > 2tp ELEC 7770: Advanced VLSI Design (Agrawal)

10. Transient Load Voltage VL(t) = 1 – a Rg [ t – CdRg (1 – e – t/T) ], 0 < t < tp T = Cd (Rg + Rd) ELEC 7770: Advanced VLSI Design (Agrawal)

11. Realizing Decoupling Capacitor VDD VDD OR S B D S B D GND GND ELEC 7770: Advanced VLSI Design (Agrawal)

12. Capacitance Cd = γ×WL×ε×ε0/Tox ≈ 0.26fF, for 70nm BSIM L = 38nm, W = 200nm γ = 1.5462 ε = 4 ELEC 7770: Advanced VLSI Design (Agrawal)

13. Leakage Resistance Igate = α× e – βTox×W where α and β are technology parameters. Rd = VL(t)/Igate Because V(t) is a function of time, Rd is difficult to estimate. The decoupling capacitance is simulated in spice. ELEC 7770: Advanced VLSI Design (Agrawal)

14. Power-Ground Layout Solder bump pads Vss Vss Vdd M5 Vdd/Vss supply Vdd/Vss equalization M4 Via Vss Vdd Vdd ELEC 7770: Advanced VLSI Design (Agrawal)

15. Power Grid + – ELEC 7770: Advanced VLSI Design (Agrawal)

16. Nodal Analysis V2 g2 g1 g3 Vi V1 V3 g4 Ci Apply KCL to node i: 4 ∑ (Vk – Vi) gk – Ci ∂Vi/∂t = Bi k=1 Bi V4 ELEC 7770: Advanced VLSI Design (Agrawal)

17. Nodal Analysis G V – C V’ = B Where G is conductance matrix V is nodal voltage vector C is admittance matrix B is vector of currents V(t) is a function of time, V(0) = VDD B(t) is a function of time, B(0) ≈ 0 or leakage current ELEC 7770: Advanced VLSI Design (Agrawal)

18. Wire Width Considerations • Increase wire width to reduce resistance: • Control voltage drop for given current • Reduce resistive loss • Reduce wire width to reduce wiring area. • Minimum width restricted to avoid metal migration (reliability consideration). ELEC 7770: Advanced VLSI Design (Agrawal)

19. A Minimization Problem Minimize total metal area: n n A = ∑ wi si = ∑ | ρ Ci si2 | / xi i=1 i=1 Where n = number of branches in power network wi = metal width of ith branch si = length of ith branch ρ = metal resistivity Ci = maximum current in ith branch xi = voltage drop in ith branch Subject to several conditions. ELEC 7770: Advanced VLSI Design (Agrawal)

20. Condition 1: Voltage Drop Voltage drop on path Pk: ∑ xi ≤ Δvk i ε Pk Where Δvk = maximum allowable voltage drop on kth path ELEC 7770: Advanced VLSI Design (Agrawal)

21. Condition 2: Minimum Width Minimum width allowed by fabrication process: wi = ρ Ci si / xi ≥ W Where wi = metal width of ith branch si = length of ith branch ρ = metal resistivity Ci = maximum current in ith branch xi = voltage drop in ith branch W = minimum line width ELEC 7770: Advanced VLSI Design (Agrawal)

22. Condition 3: Metal Migration Do not exceed maximum current to wire-width ratio: Ci / wi = xi /(ρsi) ≤ σi Where wi = metal width of ith branch si = length of ith branch ρ = metal resistivity Ci = maximum current in ith branch xi = voltage drop in ith branch σi = maximum allowable current density across ith branch ELEC 7770: Advanced VLSI Design (Agrawal)

23. Decoupling Capacitance Rg VDD + – Cd I(t) ELEC 7770: Advanced VLSI Design (Agrawal)

24. Decoupling Capacitance Initial charge on Cd, Q0 = Cd VDD I(t): current waveform at a node T: duration of current Total charge supplied to load: T Q = ∫ I(t) dt 0 ELEC 7770: Advanced VLSI Design (Agrawal)

25. Decoupling Capacitance Assume that charge is completely supplied by Cd. Remaining charge on Cd = Cd VDD – Q Voltage of supply node = VDD – Q/Cd For a maximum supply noise ΔVDDmax, VDD – (VDD – Q/Cd) ≤ ΔVDDmax Or Cd ≥ Q / ΔVDDmax ELEC 7770: Advanced VLSI Design (Agrawal)