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Statistical Framework for Technology- M odel-Product Co-Design and Convergence

Statistical Framework for Technology- M odel-Product Co-Design and Convergence. Design Automation Conference June 6 , 200 7. Choongyeun Cho † , Daeik Kim † , Jonghae Kim † , Jean-Olivier Plouchart ‡ , Robert Trzcinski ‡

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Statistical Framework for Technology- M odel-Product Co-Design and Convergence

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  1. Statistical Framework for Technology-Model-ProductCo-Design and Convergence Design Automation Conference June6,2007 • Choongyeun Cho†, Daeik Kim†, Jonghae Kim†, Jean-Olivier Plouchart‡, Robert Trzcinski‡ • †IBM Semiconductor R&D Center‡IBM T.J. Watson Research Center 29-2ebff_ver2007_06_06_05:18

  2. Overview • Motivation • Current / proposed approaches • Proposed methodology • Statistical framework for tech-model-product co-design • Application • RF product development in three evolving 65nm SOI technologies • Conclusions • Summary and contributions

  3. Overview • Motivation • Current / proposed methodologies • Proposed methodology • Statistical framework for tech-model-product co-design • Application • RF product development in three evolving 65nm SOI technologies • Conclusions • Summary and contributions

  4. Migration P0 P0 Product Model Inter-pretation T0 T1 Model (Inter-pretation) Model Bench-mark B0 B0 Migration Mask delivery Measure Measure Feedback Feedback Gen 1 Node 1 Process Preparation Mask FEOL BEOL Prep Mask Gen 2 Node 0 Time Current IC Development • Process, model and product are developed in parallel Difficult to link from product to model/process

  5. Model Process Current IC Development • Ring oscillator (RO) is common vehicle for model calibration and product benchmarking, yet may not capture complex operation of product circuit Benchmark Interpretation Feedback Co-Design Measurement Model Measurement Model Product Feedback Interpretation

  6. Proposed Approach • Statistical framework • Process variability is statistical by nature • Measurements from manufacturing-in-line electrical tests are exploited • Hardware data is capable of capturing complicated behavior of product • Systematic perspective for co-design • Translation from one component to another leading to rapid convergence of tech-model-product • Benefits • Accelerate yield learning • Reduce time-to-market and development cost

  7. Overview • Motivation • Proposed methodology • Statistical framework for tech-model-product co-design • Cross-correlation analysis • Statistical yield estimation • Variability decomposition • Application • Conclusions

  8. Cross-Correlation Analysis • Correlate circuit performance with device parameters • Large volume of in-line electrical test data is often available • Links device characteristics to product performance/yield • For highly correlated parameters, analyze sensitivity • For example: Fosc vs Vth samples from one lot xcorr=85% Product FOM (Fosc) Sensitivity=3GHz/V Device characteristic (Vth)

  9. Cross-Correlation Analysis • Statistical significance is determined: • E.g. 90% sample correlation using 60 chips guarantees84~94% correlation range within 95% confidence interval • Once most correlated device characteristics are identified, the information is fed to: • Design side: make more tolerable to the device parameter (Design-for-yield) • Technology side: control and monitor a particular process • Model side: model-to-hardware correlation (MHC) and calibration

  10. Statistical Yield Estimation • “Performance (parametric) yield” defined as probability that predefined design specs are met: • Using simulation or hardware data, estimateperformance yield • Fit design parameter samples with simple (Gaussian) distribution • Yield is predicted as:Yield(x) = 1 – CDF(x) where x=minimum design requirement

  11. Statistical Yield Estimation • Example: a static inverter-based RO in 90nm tech • Target max delay=15ps, target max active current=1mA Yield=90% Delay Delay

  12. Variability Decomposition • Decompose process variation in die-to-die andwafer-to-wafer components: • Using only a collection of manufacturing electrical test data • No physical model for process variation • Benefits: • Allow quick visualization and analysis of systematic variability • Monitor lot characteristics, and impact of process recipe change • Efficient sampling for measurement (Details available in Cho, et al., ISQED’07)

  13. Variability Decomposition Collection of in-line test data (FET’s, SRAM, cap, etc) Standardize • Utilize principal component analysis (PCA) • Can generalize for other variation ranges (within-die andlot-to-lot) • Fast run-time Screen data Find first PC for D2D variation Find first PC for W2W variation Take PC with larger variance Process variation Subtract this PC space from original data

  14. Variability Decomposition Example • Input: 1000+ parameters (FET, RO, cap, res, …) in65nm SOI tech 1stW2W PC 30 2nd W2W PC 3rd W2W PC 20 10 Systematic variation 0 -10 -20 0 5 10 15 Most dominating die-to-die variation Wafer index First three wafer-to-wafer variations

  15. Overview • Motivation • Current / proposed methodologies • Proposed methodology • Statistical framework for tech-model-product co-design • Application • RF product development in three evolving 65nm SOI technologies • Conclusions • Summary and contributions

  16. Application: Background • Current-mode logic (CML) current-controlled oscillator (ICO) was developed • Critical function block in microprocessor clocking • Migrated from 90nm to 65nm • Challenging design issues: reduced Vdd headroom, increased nonlinearity/variation/leakage.

  17. corr=98% Product Design Decision • Device tuning via statistical measurements • Floating body (FB) vs body contacted (BC) in differential pair NFETs FB Gen1 FB Correlation=98% Gen1 BC 27% boost FB BC BC

  18. Cross-Correlation Analysis • Identified critical process variation • Threshold voltage correlated with Fosc reduced Gen3 xcorr=13% Gen2 xcorr=94%

  19. Variability Decomposition • Dominant die-to-die variations analyzed forthree tech generations • Visualize how technology stabilizes. Generation 1 (Pre-production) Generation2 Generation3

  20. Statistical Yield Estimation • Predicted yield for three generations • Calculated with Gaussian PDF fits 100 Gen 1 BC 99 % Gen 1 FB 80 64 % Gen 2 47 % 60 Gen 3 Performance yield (%) 40 20 0.3% Target=12GHz 0 8 10 12 14 16 18 Fosc (GHz)

  21. Application Summary • ICO of 64-bit processor developed using proposed method across three 65nm tech generations, and met design specs in nominal and variation 15 Target Fosc=12GHz (%) Fosc 10 Mean Fosc (GHz) /µ 10 8 Fosc Target Std=8% s 6 Both Fosc,Std failed Fosc passed, Std failed Fosc,Std passed Target Gen1 Gen2 Gen3

  22. Overview • Motivation • Current / proposed methodologies • Proposed methodology • Statistical framework for tech-model-product co-design • Application • RF product development in three evolving 65nm SOI technologies • Conclusions • Summary and contributions

  23. Conclusions • A simple statistical framework is presented to expedite co-design of tech-model-product, based on three tools: • Cross-correlation analysis: identifies device characteristicsmost related/sensitive to product performance • Statistical yield estimation: predicts yield based on HW data • Variability decomposition: separates systematic variabilityfor analysis and visualization • Case study: ICO of microprocessor • Yield enhancement from 47% to 99% over three 65nm tech generations

  24. Thank you.

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