1 / 15

Glitch-Free Design of Low Power ASICs Using Customized Resistive Feedthrough Cells

Glitch-Free Design of Low Power ASICs Using Customized Resistive Feedthrough Cells. 9th VLSI Design & Test Symposium – VDAT ’05 Bangalore, August 10-13, 2005. Motivation. Application Specific Integrated Circuit (ASIC) chips employ standard cell design style.

tuan
Download Presentation

Glitch-Free Design of Low Power ASICs Using Customized Resistive Feedthrough Cells

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Glitch-Free Design of Low Power ASICs Using Customized Resistive Feedthrough Cells 9th VLSI Design & Test Symposium – VDAT ’05 Bangalore, August 10-13, 2005 Uppalapati et al.: VDAT'05

  2. Motivation • Application Specific Integrated Circuit (ASIC) chips employ standard cell design style. • Dynamic power consumed by glitches in a CMOS circuit, though significant, can be reduced or eliminated by design. • Existing glitch reduction techniques demand customized gate design, not suitable for a standard cell ASIC. Uppalapati et al.: VDAT'05

  3. Power Dissipation in CMOS Logic (0.25µ) Ptotal (0→1) = CL VDD2 + tscVDD Ipeak+VDDIleakage CL %75 %20 %5 Uppalapati et al.: VDAT'05

  4. Prior Work: Hazard Filtering Reference: V. D. Agrawal, “Low Power Design by Hazard Filtering”, VLSI Design 1997. • Glitch is suppressed when the inertial delay of gate exceeds the differential input delay. 2 or 1 or3 2 Filtering Effect of a gate 2 Uppalapati et al.: VDAT'05

  5. Prior Work: A Reduced Constraint Set LP Model for Glitch Removal Reference: T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program,” VLSI Design 2003. • Satisfy glitch suppression condition at all gates: Differential path delay at gate input < inertial delay • Use a linear program (LP) to find delays • Path enumeration avoided • Reduced (linear) size of LP allows scalability • Design gates with specified delays • 40-60% dynamic power savings in custom design • Procedure is not suitable for pre-designed cell libraries Uppalapati et al.: VDAT'05

  6. Prior Work: ASIC • J. M. Masgonty, S. Cserveny, C. Arm and P. D. Pfister, “Low-Power Low-Voltage Standard Cell Libraries with a Limited Number of Cells”, PATMOS ’01 • Transistor sizing results in 20 - 25% savings in power • Power optimized by minimizing parasitic capacitances • No glitch reduction attempted • Y. Zhang, X. Hu and D. Z. Chen, “Cell Selection from Technology Libraries for Minimizing Power”, DAC ’01 • Mixed Integer Linear Program (MILP) to select from different realizations of cells such that power consumption is minimized without violating delay constraints • Sum of dynamic and leakage power is minimized • Library contains cells of varying sizes,supply voltages, and threshold voltages • Achieved 79% power saving on an average • No glitch reduction attempted. Uppalapati et al.: VDAT'05

  7. New Glitch Removing Solution • Balanced the differential delays at cell inputs: • Using delay elements called Resistive Feedthrough cells • Automated the delay element • Generation • Insertion into the circuit Uppalapati et al.: VDAT'05

  8. Comparison of Delay Elements • Resistor shows • Maximum delay • Minimum power and area per unit delay • Hence, best delay element • Resistive feed through cell • A fictitious buffer at logic level III. Polysilicon resistor I. Inverter pair II. n diffusion capacitor IV. Transmission gate Uppalapati et al.: VDAT'05

  9. Resistive Feedthrough Cell • A parameterized cell • Physical design is simple – easily automated • No routing layers(M2 to M5) used – not an obstruction to the router R□*(length of poly) R = Width of poly S. Uppalapati, “Low Power Design of Standard Cell Digital VLSI Circuits,” Master’s Thesis, Rutgers University, Dept. of ECE, Piscataway, NJ, Oct. 2004. Uppalapati et al.: VDAT'05

  10. R Vin Vout CL TPLH + TPHL TP = 2 RC Delay Model • CL varies during transition (model not perfectly linear) • Spectre simulation data stored as a 3D lookup table • Average of signal rise and fall delays • Linear interpolation used TP CL R Uppalapati et al.: VDAT'05

  11. Design Optimization Flow Design Entry Find delays from LP Find resistor values from lookup table Tech. Mapping Remove Glitches Generate feed through cells and modify netlist Layout Uppalapati et al.: VDAT'05

  12. Results S. Uppalapati, “Low Power Design of Standard Cell Digital VLSI Circuits,” Master’s Thesis, Rutgers University, Dept. of ECE, Piscataway, NJ, Oct. 2004. Uppalapati et al.: VDAT'05

  13. Glitch Elimination on net86 in 4bit ALU Source: Post layout simulation in SPECTRE Uppalapati et al.: VDAT'05

  14. Layouts of c880 Power saving = 43% Area increase= 98% Original layout of c880 Optimized layout of c880 Uppalapati et al.: VDAT'05

  15. Conclusion • Successfully devised a glitch removal method for the standard cell based design style • Does not require redesign of the library cells • Does not increase the critical path delay • Modified design flow maintains the benefits of ASIC • On an average • Dynamic power saving: 41% • Area overhead: 60% • Possible ways to reduce area overhead • Cell replacements from existing library • On-the-fly-cell design • Adjust routing delays for glitch suppression Uppalapati et al.: VDAT'05

More Related