Review for Final: CPE 329 Spring 2007

1. Review for Final: CPE 329 Spring 2007 • Lectures 1-14, Therac-25, Chapters 1 & 2, Labs 1-5 • Exam Review Outlines • Homework problems • ISE/EDK technology • Digilent Nexys board and peripherals technology • Not held accountable for specifics of Digilent D2FT-DIO5 technology, just principles • No coding, just pseudo code (no syntax) • One page (both sides) of reference notes • Calculator

2. Exam Review Outline: lecture 1CPE 329 Overview • Course Description • Course Learning Objectives • Topics Covered • Prerequisite material • Course Material • Lab Overview • Development Environment (CAD Tools) • Lab Equipment • Processor • Lab Experiments • Experiment 1 Hardware-Based Digital Clock • Experiment 2 MicroBlaze “Hello World!” • Experiment 3 Microcontroller-Based Digital Clock • Experiment 4 Function Generator • Experiment 5 Final Design Project

3. Exam Review Outline: lecture 2Introduction to Digital Systems • Taxonomy of Digital Systems • Advantages and Disadvantages of each category (Cost, performance, ease of design, customization, configurability, integration, number of transistors) • Semiconductor Technology Trends • Moore’s Law Number of transistors per die doubles every couple of years (historical data) http://www.intel.com/research/silicon/mooreslaw.htm • ITRS Future Projection • Increase in the number of practicing engineers per year • Must work at higher levels of abstraction • Increasing levels of abstraction for HW and SW • Hardware Software Co-design

4. Homework • In class we talked about field and factory programmable gate arrays. Which type of gate array would have better performance? State the two primary reasons given in class that one will perform better than the other. • Hardware-based implementations typically have a performance benefit over stored-program digital systems. Explain why this is true? • Given that hardware-based implementations typically have a performance benefit over stored-program digital systems give three reasons that most embedded systems use either microprocessors or microcontrollers? • VHDL Alarm Clock • Using the clock you designed for lab 1 we would like to add an alarm function. The system requirement for the alarm function is to use another pushbutton to enter alarm mode. In alarm mode the alarm time should be displayed on the LCD and the hours and minutes pushbuttons should advance the hours and minutes of the alarm setting just as it did while setting the clock. There will be a module that asserts a logic signal called BUZZ if the current time matches the alarm time. • Reusing the modules that you used for lab 1 (Time_Keeper, Arbiter, and HEX2BCD as shown in the figure on the following page) draw a hardware diagram with the additional modules needed to add the alarm function and briefly describe (1-2 sentences / module) how each block should function. • In the first lab many students noticed that it was cumbersome to set the clock if the minutes and hours incremented every second during the set function. Determine how to have the set function increment every 0.5 seconds. Assume that you are supposed to minimize the changes to your current design and you can only use one system clock. Be sure to describe the conditions that are needed to increment the seconds, minutes, hours, and am/pm when in timekeeping mode. • In the lab we designed a Digital Clock using VHDL that was clocked with a 50MHz Epson oscillator. The frequency tolerance for the oscillator is: ∆f/f = +/- 50x10-6. Explain what are the sources of error in your digital clock and determine the maximum error that the clock would have after running for 1 day.

5. Homework • VHDL Design: Analyze the following VHDL code to answer the questions below: entity state_machine is port( clk,S : in std_logic; z :out std_logic ); end state_machine architecture design of state_machine is signal NS : std_logic_vector ( 1 downto 0) :=”00”; begin synch_proc: process (clk, S) begin if (clk’event and clk=’1’) then if(S=0) then if (NS = “00”) then NS <= “01”; elsif(NS = “01”) then NS <= “10”; elsif(NS = “10”) then NS <= “11”; elsif(NS = “11”) then NS <= “00”; endif; endif; endif; end process synch_proc; z <= NS(1); end design; a. Draw the State Diagram for the VHDL code:_________________________________ b. Complete the ModelSim simulated output for the state_machine circuit.______________ c. Describe the function of the state_machine circuit? ____________________________

6. Homework • In the “Introduction to Digital Systems” chapter of the supplemental material digital systems were first divided into two different categories. List the two categories and identify which one generally has higher performance. Also explain why this type of digital system has higher performance? • Does a factory programmed gate array or a field programmable gate array typically have better performance? List two factors that contribute to a performance advantage of one over the other. • You are asked to implement an algorithm using the tools available to you in the CPE 329 lab. The application requires the highest-performance design that you can download into the Digilent D2FT board. You notice that the algorithm is computationally intense but does not have a significant amount of inherent parallelism. Describe which approach and design tool you would select. Also, explain why you chose this approach. • Does a factory programmed gate array or a field programmable gate array typically use more silicon die area to implement a given VHDL design? List two factors that contribute to a area advantage of one over the other.

7. Exam Review Outline – lecture 3Programmable Logic • History of Integrated Circuits • Advantages of CPLDs • Programmable Elements to connect nets or configure hardware devices • One-time-programmable (OTP) – Fuse/Antifuse • Re-programmable • Volatile (SRAM) • Non-Volatile (EEPROM, Flash) • CPLD Architecture Functional Blocks • SPLD like configurable logic • MacroCell • MacroBlock • Programmable Interconnect • I/O Blocks • FPGA Architecture • FPGA Fabric • Configurable Logic Block (Programmable MUX, Look Up Table, Pass Transistor) • Programmable Interconnect • I/O Blocks • Block RAM Memory • Hardcore blocks (ie Multipliers, PowerPC) • System on Chip (Soc) using Hardcore or Softcore Processors

8. Exam Review Outline • Programmable Interconnect (6-transistor junction) • Direct – CLB to CLB • Local • Global • Timing – Clock networks • Propagation delay timing for interconnect 1st order model • Wired interconnect tPLH • Programmable interconnect tPLH • Design Example of 8-bit Ripple Carry Adder • CPLD Design • Full Adder • FPGA Design • 2-bit adder subcomponent • LUT programming (Combining LUTs for more input variables) • Programmable interconnect • Adder Using VHDL

9. Exam Review Outline • Design Flow • Designer • Write HDL Code • Simulate • Constraints • CAD Tool • Synthesis • Translate/Map • Place and Route • Generate Programming File • Download bit file • Xilinx FPGA and CPLD • Spartan IIE FPGA Architecture • FPGA Fabric • I/O Block • CLB and CLB Slice • Product Family • CoolRunner XPLA3 Architecture • Features • Architecture Block Diagram • PLA Logic Inputs • Logic Block (MacroBlock) • I/O Cell • MacroCell • Timing Model

10. ‘1’ ‘1’ Driver Load Vin Vout Homework 1. In class we talked about the migration from discrete logic to CPLDs. State three advantages of using CPLDs over discrete components. 2. Explain the three ways that SRAM cells are used to configure the Xilinx Spartan2e FPGA. 3. Calculate the fall-time for the Driver inverter in the circuit below whose output is routed through the programmable interconnect on an FPGA. Use the values supplied in the table to approximate Rp, Rn, and CL. Use the following definition of fall time: The time from when the input changes from a low to high logic value to the time when the output reaches 0.1Vdd. (Note: ln(0.1) ≈ -2.3, ln(0.9) ≈ -0.1). Component Value Rp 22 kΩ Rn 11 kΩ CL 1x10-15 f

11. 1 0 S 4. Map the combinational function, F(X2,X1,X0)=X2 XOR X1 XOR X0, to the macroblock given below. Assume an anti-fuse programmable element in the AND-array and denote a grown fuse with an ‘X’. Indicate the configuration memory required such that F is routed as an output to the I/O pin in the figure. Assume an SRAM-based programmable element (shaded boxes) for the MUX control and use the following notation: 1 = logic high, 0 = logic low, and D = don’t care. 11 global OE 1 10 0 01 X0 X1 X2 00 0 s0 s1 F D Q Clock 1 to AND array 0 S

12. 5. (a) Given the programmable interconnect structure shown below identify the best routing from the output of CLB 1 to the input of CLB 8 to achieve the minimum interconnect delay. Do so by darkening the best route you determined. All of the programmable interconnects shown use the same type of pass transistor. You can assume the resistance in the wire is approximately zero. (b) What circuit parameters affect the interconnect delay? 6. One student in a prior class asked how are the “System Gate Equivalents” determined for FPGAs since a configurable logic block uses look up tables not logic gates for computation. Estimate how many “System Gate Equivalents” one LUT has given the following data from the Xilinx Spartan-2E Spec. Assume that all of the LUTs in an FPGA count for 10% of the System Gates. Device System Gate Range Total CLBs Slices/CLB LUT(16x1b)/Slice XC2S300E 93K – 300K 1,536 2 2 A 1 2 3 4 5 6 7 8 9 B C D E

13. Exam Review Outline – lecture 4Embedded Systems and MicroBlaze Computer System • Computer Systems, Processors, and Terminology • Custom HW – ASIC, VLSI, … • Processor vs. Microprocessor • Microcomputer vs. Microcontroller • Embedded system design process • Requirements • Specifications • Architecture • Components • System Integration • Embedded System • Characteristics: Complex Algorithms, user interface, real-time, multi-rate • Costs: Cost of goods, mfg cost, development cost • Challenges • Hardware performance vs. Cost • Code Space/ Code Density • Need to meet real-time demands • Minimize power consumption • Design for upgrade-ability • Verification • Reliability

14. Exam Review Outline • Embedded Systems Continued • Computer System Block Diagram • System on Chip –SoC • Processor in ASIC or FPGA with Softcore processor • Programmers model – Registers, Condition Codes and Instruction Set Architecture • Why is it important to know ISA? • Computer Classification • Architecture • Von Neuman / Princeton Architecture • Harvard Architecture • DSP’s • RISC vs. CISC • EDK computer system • MicroBlaze Processor • Busses (ILMB, DLMB, IOPB and DOPB) • MicroBlaze Memory System • Memory Controllers and BRAM • Memory Mapped I/O • IP Cores • GPIO Programming Input and Output Devices

15. Exam Review Outline • Base Address • Memory Mapped Registers (Data Register and Data Direction Register) • I/O Instructions • Software functions to read and write MicroBlaze memory locations • Xio_In32( ); and Xio_Out32( ); • DIO5 I/O Controller • Bus Based Interface Between FPGA and I/O Controller • Computer System • Bus Write Cycle • Timing Diagram • Algorithm to implement using GPIO and MicroBlaze • DIO5 Memory Map of I/O Devices • LCD initialization Routine • LCD Display Characters • Nexys interface to LCD and peripherals (buttons and leds)

16. Homework • Microcontrollers are often a hybrid of RISC and CISC architectures. List the characteristics discussed in lecture for each below? • At the hardware level how would the MicroBlaze CPU set an 8-bit GPIO peripheral to be an input? Describe what happens at the hardware level between the CPU and the GPIO peripheral and NOT the device driver function call. • Describe the uses of and differences between the OPB and the LMB busses? • The Spartan IIe that we are using in the lab has 8k words of BRAM memory. The BRAM is dual ported and has an address space of 0x0000 - 0x1fff. If the Instruction Memory Controller base address is set to 0x0000 and the base address for the Data Memory Controller is set to 0x1000 determine: • What physical address would be read if the MicroBlaze fetched an instruction from address 0x0100? • What physical address would be read if MicroBlaze fetched a data operand with data address of 0x1200?

17. Homework • The following code is similar to the code in the blinker tutorial and shows how to set the lower 8 LEDs on the DIO5 board. Show how the code should be changed to read the lower 8 pushbuttons and store the result into the pb variable. Xuint32 XGpio_DiscreteRead (XGpio *InstancePtr, unsigned Channel) Read state of discretes for the specified GPIO channnel. Parameters: InstancePtr is a pointer to an XGpio instance. Channel contains the channel of the GPIO (1 or 2). Returns: Current copy of the discretes register. #define BtnLowAddr 0x00 #define BtnHighAddr 0x01 #define LedLowAddr 0x00 #define LedHighAddr 0x01 main(){ XGpio led_gpio, data_gpio, addr_gpio, cs_gpio, oe_gpio, we_gpio; unsigned pb; XGpio_Initialize(&data_gpio, XPAR_DIO_DATA_DEVICE_ID); XGpio_Initialize(&addr_gpio, XPAR_DIO_ADDR_DEVICE_ID); XGpio_Initialize(&cs_gpio, XPAR_CS_N_DEVICE_ID); XGpio_Initialize(&oe_gpio, XPAR_OE_N_DEVICE_ID); XGpio_Initialize(&we_gpio, XPAR_WE_N_DEVICE_ID); XGpio_SetDataDirection(&addr_gpio, 1, 0); XGpio_SetDataDirection(&cs_gpio, 1, 0); XGpio_SetDataDirection(&oe_gpio, 1, 0); XGpio_SetDataDirection(&we_gpio, 1, 0); XGpio_SetDataDirection(&data_gpio, 1, 0); XGpio_DiscreteWrite(&oe_gpio, 1,1); XGpio_DiscreteWrite(&cs_gpio, 1,0); XGpio_DiscreteWrite(&we_gpio, 1,0); XGpio_DiscreteWrite(&addr_gpio, 1,LedLowAddr); XGpio_DiscreteWrite(&data_gpio, 1,0xAA); XGpio_DiscreteWrite(&we_gpio, 1,1) XGpio_DiscreteWrite(&cs_gpio, 1,1); }

18. Homework • What type of applications would benefit from a processor with a Harvard architecture? Explain how the application benefits from a processor with a Harvard architecture. • Describe the uses of and differences between the OPB and the LMB busses? • Draw a timing diagram that shows a read of the lower 8 pushbuttons through the DIO5 I/O Controller. Include all of the logic signals that connect to the DIO5 Board. You can assume that the pushbutton 4 is pushed and the rest of the pushbuttons are not pressed. • What is the difference between a Harvard and Von Neumann/Princeton architecture? What type of architecture does the MicroBlaze use? • MicroBlaze Memory System: Draw the architecture of the MicroBlaze memory system used in Experiments 2 and 3. Provide values for base address registers where applicable. • I/O Controller Bus Cycles: In Experiments 2 and 3 you configured the MicroBlaze system with five GPIOs for the data bus, the address bus, and three control signals to communicate with the I/O Controller programmed in the CoolRunner CPLD on the DIO5 board. Write a C function turn_on_leds() that will turn on all 16 LEDs on the DIO5 board using this same MicroBlaze system. The header file for the xparameters.h and the DIO5 Default Circuit Memory Map are provided on the next page. • In Experiments 2 and 3 you configured the MicroBlaze system with five GPIOs for the data bus, the address bus, and three control signals to communicate with the I/O Controller programmed in the CoolRunner CPLD on the DIO5 board. Write a C function display_message() that will write “CPE 329!” to the LCD screen. on the DIO5 board using this same MicroBlaze system. You may call the function configure_LCD() to initialize the LCD screen and configure it for entry mode. You can use the header file xparameters.h provided for lab 2 and 3. • You need to select either a PowerPC (RISC) or Motorola 68000 (CISC) microcontroller for a particular design application. Both have adequate performance and comparable cost. The application will require external memory so minimizing the code space is critical. Which microcontroller will you select? Explain why you selected the microcontroller that you did.

19. Homework • Ace engineer proposes writing a high performance OPB bus. Ace’s goal is to create an OPB bus equivalent with all of the same functionality as currently is available but allow single cycle bus transactions. Are these goals feasible? If so, describe one way the OPB bus performance can be improved. • If our development board was running at 100MHz and the Xio_Write32() and Xio_In32() functions calls only take one clock cycle to execute, then would we need to make any changes in our bus read cycle code? Refer to the information in the DIO5 reference manual? • You are asked to add a second DIO5 board to the lab setup so that you have two LCD displays to output messages. Now you are required to write “Hello World!” onto one screen as before, and write “CPE 329 Rules!” on the other LCD Screen. Your design requirements include using the fewest number of Slices and Code space as before. • Draw the system architecture for the new system. Be sure to include the number of bits for each GPIO device. • Describe how the code would have to change to accommodate the new hardware system and requirements as compared to the default computer system in the tutorial. Your answer can be in bullet format but you must use sufficient detail to carefully describe the software algorithms. • Given the MicroBlaze memory map used in the blinker tutorial for the computer system write the minimum amount of “C” code to only light the lower four LEDs on the DIO5 board. Do not use any pound defined words in your code (use hex numbers for function parameters) or assume any initialization has been done.

20. Exam Review Outline – lecture 5Xilinx Embedded Developers Kit • Embedded Developers Kit Design Flow • Hardware System • Add Cores • Bus Connection • Memory Map • Port Connections • Parameters • User Constraints • Software System • Device Driver Interface (Xio_Out, Xio_In, …) • Main Code using “C” • Compile • Generate Bitstream • Update Bitstream • Download code

21. Homework • When using the EDK explain what happens when you execute the following commands? • Generate Netlist? • Generate Libraries? • Update BitStream? • Describe what happens in the mapping stage of the Hardware design flow? Describe what the input is for the mapping process and what is generated by the mapping process. • You are asked to implement an algorithm using the tools available to you in the CPE 329 lab. The application requires the highest-performance design that you can download into the Digilent D2FT board. You notice that the algorithm is computationally intense but does not have a significant amount of inherent parallelism. Describe which approach and design tool you would select. Also, explain why you chose this approach.

22. Exam Review Outline – lecture 6MicroBlaze Instruction set, Architecture, Performance, and Interrupts • MicroBlaze • Programmers Model • Data Types • Instruction Set • Program Counter and Machine State Register • General Purpose Registers • Instruction formats • Big Endian / Little Endian • Pipelining • Overlapped execution • Performance (Latency, throughput, IPC, and CPI) • MicroBlaze Pipeline (F->D->Execute) • Data Dependency Hazards • Control Hazards • Delayed Branches

23. Exam Review Outline – lecture 7Timers and Counters Interrupts • Asynchronous event that allows device to interrupt CPU and transfer control over to an interrupt service routine. • Foreground task (main loop) • Interrupt Service Routing (ISR) or Interrupt Handler • Interrupt and Acknowledge • Hardware interface for interrupt • Interrupt process at HW level • CPU Initializes and enables interrupt device and unmasks interrupts • External Interrupt request generated • Possibly on chip peripheral device • Possibly external device • CPU typically finishes current instruction • Some instructions are interruptible • Some CPU’s perform HW context save (if not context save is responsibility of ISR) • CPU’s typically disable interrupts automatically • Return address stored (on stack or in dedicated register) • Branch to interrupt service routine: Fetch Interrupt Vector (address of interrupt service routine) or address of instruction in Jump table and put this address into the PC • Execute the interrupt service routine • ISR must clear interrupt flag (acknowledge interrupt) • Restore Context if not handled in HW • RTI - Return from interrupt instruction :Restores CPU context including condition codes and Branches to return address • Debugging with interrupts • Multiple Interrupts and Interrupt Priorities • Maskable vs. Non-Maskable interrupts • Handling multiple interrupts using an OR gate • Interrupt controllers and multiple interrupt devices • Interrupt overhead • Comparison of Interrupts to Polling algorithms

24. Homework 1. Determine the number of cycles from the time the first SUB instruction is fetched until the last BNE instruction completes execution and the CPI for the following MicroBlaze assembly code if the BNE branch is taken 1 times? Assume the SUB instruction execution stage takes 1 cycle to execute and the BNE takes the number of cycles described in lecture. Loop: SUB r3, r3, 1 SUB r1, r1, 4 SUB r2, r2, 8 BNEI r3, loop_offset 2. The semantics for the MicroBlaze Instruction BEQ and BEQD are both the same {if Ra=0: PC:=PC + Rb}. What is the difference between the two branch instructions? When would BEQD be used and why would it? Be specific. 3. List three specific items that contribute to interrupt overhead. 4. Explain why the EDK has an Interrupt Controller IP Core? Be certain to discuss the advantages that the Interrupt Controller IP Core would have compared to the simple “OR” gate approach discussed in lecture. 5. Determine the state of the carry bit and the Registers R1, R2, and R3 after the following MicroBlaze assembly instruction is executed if R1 = 0x0f000000, R2 = 0xff000000, R3 = 0x8f000000 and C=0 before the instruction is executed. Also show the RTL description of the instruction. ADDKC R1, R2, R3

25. Exam Review Outline – lecture 8Digital-to-Analog Conversion and Analog-to-Digital Conversion • Sampling theory • Sampling Frequency • Resolution • Analog-to-Digital Converters • Sample and Hold • Summing op-amp circuit • Digital-to-Analog Converters • Analog Devices AD7303 Architecture • AD7303 IP Core and device drivers • Software for digital-to-analog conversion • Digilent AIO1 Interface Board setup and schematic • Interfacing Sensors • Resolution and Selection of VREF • ADC digital output • LM35 Temperature Sensor

26. Homework 1. Use C code (or psuedocode) to set the AIO1 DAC A output to 2V if Vref=5V? You can assume the MicroBlaze DAC core has a base address of DAC_BA and the board is configured as used for Experiment 4. 2. List three ways in which you could reduce the error in the output waveforms that you generated in Experiment 4 using the DAC on the AIO1 Board. 3. Design a minimal (with respect to hardware resources) MicroBlaze system using only OPB GPIO and OPB Timer/Counter cores on the DOPB that would perform the same function as a system using the AD7303 Core to interface to the AD7303 DAC. Provide the architecture and describe any required software for your system. 4. You are designing a Water Height Measurement System that provides the height of the water in a 100 foot tall water tank. Your system must be accurate to 0.5 feet. You are given a water height sensor that has an output of 10mV/foot and 0V at 0 feet. (a) Determine the ADC resolution needed for this project? (b) Determine the smallest A/D Converter (number of bits) that can meet this requirement from the following list (4-bit, 8-bit, or 16-bit). Show your work to justify your answer. (c) Determine how to set the Voltage Range {VRange_Low and VRange_High} for this system. (d) What would be the ADC values returned for 0 feet and 60 feet?

27. Exam Review Outline – lecture 9Serial I/O and Programming Input and Output • Data Management • FIFO • Stack • Software Implementation of FIFOs and Stacks • I/O Algorithms for UART with Keyboard and Monitor Algorithm • I/O with busy waiting and Memory Mapped I/O • How it works • Algorithm (flow chart) • C code implementation • I/O with interrupts • I/O Buffer Queue • With separate input and output device interrupt handlers that can run at different speeds we need a place to store incoming data. • FIFO or circular queue • Head and tail pointers • Storing and removing characters • Queue empty, queue full, number of characters in queue • How it works • Algorithm (flow chart) • C code implementation • Task processing with ISRs

28. Homework • How is data transferred from one UART to another without a Clock? Draw the timing diagram and indicate the relevant timing information. • If a CPU is running at 100 MHz and has a CPI of 1.2, how many CPU instructions could be executed for each byte of data sent using a UART at 9600 baud? • You are designing a system with a CPU and three external devices. External device 1 and 2 are input devices and external device 3 is an output device. Each external device has two memory mapped registers (Di_DATA and Di_STATUS) and one interrupt output signal (Di_INT). The status registers are used the same way as shown in lecture. The external devices have an address, data and control bus. The CPU has one interrupt input signal, INT and the address, data and control busses that are used to connect to the external devices. • Draw a hardware diagram of an interrupt driven system that includes the CPU and the three external devices? You can only use the CPU, external devices and discrete logic gates. Be certain to include the interrupt signals and bus signals. • For the system in part (a) design an algorithm (flow chart) for an interrupt handler that will take an interrupt generated by any of the three external devices. The interrupt handler should use a queue to hold incoming characters as was used in the interrupt driven example that was presented in lecture. You can neglect a buffer full error, device priorities, and concern about starvation.

29. Exam Review Outline – lecture 10Other I/O Devices • Switches and Pushbuttons to digital logic (circuit and resistance) • Debouncing Switches and Pushbuttons • SR latch • RC filter • Software Debounce algorithm • Keypad • Direct wired keypad • Matrix keypad • Operation • benefit • Keyboard • PC Keyboard (microcontroller, serial interface, scan codes) • PS2 port • Bidirectional Clock and data • Master Slave • Communication with Keyboard and Host • Timing diagram • Scanned Keyboard: Benefits and Issues • Mouse • Unidirectional • Timing diagram • Touch-screen Displays • Vertical and Horizontal Position

30. Exam Review Outline • LEDs • I-V Characteristics • Circuit and current limiting resister • 7-Segment Displays • 7-segment code • Circuit elements • Raster scan • Cathode Ray Tube (CRT) • Directly driven (Data, Horizontal and Vertical Deflection) • Frame buffer device driver • VGA Controller • Interface/Connector • Video RAM • Character LCD Displays • Controller and LCD • Addressing Modes • ASCII Characters • DRAM Buffer • Font Table • Hardware interface • Graphical LCD Displays • Pixel by Pixel Control RGB

31. Exam Review Outline – lecture 11Other Peripheral Devices: External Memory controller and Serial Peripheral Interfaces • External memory controllers • SRAM structure • SRAM memory block – data-in and data-out busses, bidirectional data bus • Memory read and write signals – proper assertion of control signals • OPB EMC core • Parameter configuration • Register model • Timing of read and write cycles • Serial peripheral Interface • Four concepts: Serial, synchronous, Master-slave protocol, data exchange • IO signals • Master-slave configuration • SPI mode • Clock polarity • Clock phase • OPB SPI core • SCK, slave select, MOSI, MISO signals • Register model

32. Homework 1. With the OPB External Memory Controller parameters configured as given below, what physical memory location(s) is(are) accessed by the call XIo_Out32(0x11000004, 0x12345678) and what is/are the contents after the call? Must other parameters be set? If so, what are they and how would they affect the result of the function call? Parameter NameValue C_NUM_BANKS_MEM 2 C_MEM0_BASEADDR 0x00100000 C_MEM1_BASEADDR 0x11000000 C_MEM0_HIGHADDR 0x0010FFFF C_MEM1_HIGHADDR 0x11FFFFFF C_MEM0_WIDTH32C_MEM1_WIDTH 8 2. Compare and contrast the functionality of the UART and SPI devices. Provide one application for each device that could not be used by the other.

33. Exam Review Outline – lecture 12Power Consumption and Energy • Heat Generation depends on Power Consumption • Battery Life depends on Energy Consumption • In CMOS what causes power consumption • Static • Leakage Current • Sub Threshold Current • Passive Current dissipation • Dynamic • Switching Current • Charging and Discharging Capacitive loads • Pcap = CeffVdd2f, Ecap = CeffVdd2 • Methods to Reduce Power and Energy Consumption • Power management • Static • Dynamic • Power management state machines • StrongARM Example

34. Exam Review Outline – lecture 13Survey of Microcontroller Market and Common Microcontrollers • Microcontroller market segments • Microcontrollers vs. Microprocessors • Market analysis • Alternate Microcontroller Devices • PIC • Atmel • Mot HC12 • Mot 68000 • DSPs • Applications • What is a digital signal processor • TMS 320 • DSP5600

35. Exam Review Outline – lecture 14Ethics in Engineering • IEEE Code of Ethics • Engineering ethics issues • Cheating • Responsibility • Scapegoating • Intellectual Property • Whistle Blowing • Outsourcing • Layoffs • Engineering integrity • Conflict of interests • Gifts • Product Readiness • Discrimination • Therac-25 Case • Players • Incidents • In-class group discussion

36. Homework 1. What ethics issues have you encountered while in school? How have you handled them? Do you expect to handle these ethics issues differently if working in industry? 2. In Digital Design you learned to take advantage of don’t care inputs in a Boolean expression in order to minimize the cost (where cost = # gates + # gate inputs) of its circuit realization. Are there any ethical issues associated with doing this if you were to design a BCD to 7-segment decoder in lab? Are there any ethical issues associated with doing this if you were to design a subcomponent for a new Therac-25?