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CALYPSO

CALYPSO. HERCROM xx G2. Albin-zhang@ti.com Texas Instruments Shanghai Wireless Customer Integration & Design Center. Calypso General Description. Calypso General Description. * DO NOT COPY *. GSM/GPRS (class 12) capability

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CALYPSO

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  1. CALYPSO HERCROMxxG2 Albin-zhang@ti.com Texas Instruments Shanghai Wireless Customer Integration & Design Center

  2. Calypso General Description Calypso General Description * DO NOT COPY *

  3. GSM/GPRS (class 12) capability Full-Rate(FR), Enhanced Full-Rate(EFR), Half-Rate(HR), Adaptive Multi-Rate(AMR(for C035)) speech coding capability 2 Processor Cores: ARM7TDMIE: 0~39MHz(0~52MHz for C035) DSP TMS320C54x: 0~91MHz (0~104MHz for C035) For the structural test of the logic (full-SCAN, BIST, MT,JTAG boundary-SCAN). 179-PINmStarBGA Calypso General Description

  4. GPRS Digital Base-Band

  5. CALYPSO - Overview CALYPSO OVERVIEW * DO NOT COPY *

  6. Calypso - Block Diagram

  7. Calypso - MS Signal Flow BB SIGNAL PATH CONTROL PATHS CONTROL PATHS RITA Transceiver & Synthesizer Temp. Sense SIM CARD MADC TAP IOTA ADAC SIMS BBC IR, IRX QR, QRX BCI IT, ITX QT, QTX VRPC IBIC PA_LEVEL APC VREG AFC VBC DATA CLK VSP TSP CKG BSP USP SYN_EN EN PA_ON RX900 /TX1800 Calypso RIF TSP ULPD SPI RTC MCSI RX1800 /TX900 CRYPT TPU TIMER SPI API WatchDog SIM PLL ROM LEAD TIMER1 INTH UART IRDA XIO RAM IRDA TIMER2 BRIDGE CLKM AFC Reference Oscillator KEYBOARD BRIDGE INTH DMA ARMIO ARM7 GPIOs DATA ADAPTOR FUNCTION Power Supply XO_ENA UART MODEM MEMINT PWL SRAM LPG PWT I2C uWire FLASH SRAM LCD LED BUZZER LIGHT

  8. Calypso - MEMINT Memory Interface

  9. Calypso - ARM memory interface function • External Arm memory access management: • Access Size from 8-bit up to 32-bit • Enable the connection of slow device (wait state insertion) • Memory control signal ( chip-select, write strobe generation) • Arm to API memory access management: • Support 16-bit and 32-bit API read and write access • Arm to Rhea bridge access management: • Access size adaptation for RHEA access • Arm nWAIT and access control flags generation(byte-latch, etc...).

  10. CALYPSO - ARM memory interface function DIAGRAM

  11. CALYPSO - MEMINT : Pins Description CALYPSO DATA[00..31] ADD[00..20] ADD21 FLASH nCS0 nCS1 nCS2 nCS3 CS4 ADD22 nCS5 RnW nOE nFWE nFDP nBLE nBHE SRAM ARM Memory Interface MEMORY LCD

  12. CALYPSO - MEMINT : Registers for memory interface Number of Wait State, Device data size, Write enable disable, Big/Little endian, number of Dummy Cycle

  13. Calypso - Interrupt Handler Interrupt Handler

  14. Calypso - ARM Interrupt Handler • Provides up to 21 prioritized and maskable interrupt to the ARM core. • low level or edge sensitive selectable • Flexible routing to FIQ or IRQ of ARM • 3+ N*2 cycles latency(N interrupt )

  15. Calypso - INTH ‘s registers summary

  16. Calypso - ARM Interrupts

  17. Calypso - ARM Interrupts

  18. Calypso - Pins Description of ARM Interrupt Interface IOTA Calypso ARM Interrupt Interface PWON, RPWON, Charger plug, ITWAKEUP EXT_IRQ EXT_FIQ INT2 INT1 Abnormal voltage conditions are detected.

  19. Calypso - Clocks Generator and Control CLKM

  20. Calypso - CLKM : Features • Generate and control clocks distribution to the ARM core, Lead core, internal and external peripherals. • Control reset signals of ARM core, LEAD core, internal and external peripherals. • Control deep low power mode of external FLASH

  21. Calypso - CLKM: Block Diagram

  22. Calypso - Real Time Clock Real Time Clock

  23. Calypso - RTC: Features • Time information in BCD code • Calendar Information in BCD code up to year 2099 • Interrupt generation

  24. Calypso - RTC: Block Diagram

  25. Calypso - ARM Interrupts (RTC) IRQ0 IRQ (edge) WatchDog TIMER IRQ1 IRQ (edge) TIMER1 IRQ2 IRQ (edge) TIMER2 IRQ3 FIQ (level) EXT_FIQ, TSP Rx, SIM card insertion/extraction IRQ4 IRQ (edge) TPU frame IRQ5 IRQ (edge) TPU page IRQ6 IRQ (edge) SIM IRQ7 IRQ (level) UART_MODEM or UART_IRDA IRQ8 IRQ (level) Keyboard IRQ9 IRQ (edge) RTC IRQ10 IRQ (level) RTC Alarm, ULPD GSM timer, I2C IRQ11 IRQ (edge) ULPD end of gauging IRQ12 IRQ (level) EXT_IRQ IRQ13 IRQ (edge) SPI IRQ14 IRQ (level) DMA IRQ15 IRQ (edge) API

  26. Calypso - Ultra Low Power Down Controller ULPD Controller

  27. Calypso - ULPD: Features • Maintenance of the GSM time whatever the mobile activity mode (big sleep, deep sleep, switch off) • Perform the power on/off and off/on of the chip • Gauging of an external quartz based oscillator (32kHz) to keep the time accuracy during sleep • interrupt generation to MCU

  28. Calypso - ULPD: Gauging 32 KHz Clock • Compare 32 KHz with a high frequency clock during any active period. • Compare 32 KHz with the GSM network time.

  29. Calypso - ULPD: Deep Sleep Functional block diagram on_off R

  30. Calypso – Small sleep(1) CK13Mhz ENABLE_CK13Mhz SLICER IT Alarm RTC Asynchronous WAKE_UP CLKM WatchDog INTH CK32Khz SPI ULPD MEMINT GSM time B R I D G E TIMER1 TPU RHEA bus ARM7 TSP LPG TIMER2 SIM MCU subchip PWT ARMIO PWL DMA UART IRDA uWIRE uWIRE B R I D G E API UART MODEM LMM M112L00 RHEA bus MCSI RIF INTH DSP subchip CRYPT JTAG Calypso 32KHz QUARTZ 13MHz TCXO External ARM7 Memories

  31. Calypso - Small sleep(2) • Small Sleep - VTCXO ON - ARM clock OFF - TDMA interrupt enabled • Small Sleep Wake-up Events - TDMA interrupt - ARMIO (keypad) - UART - External IRQ/FIQ (if not masked) - GSM Timer interrupt

  32. Calypso - Big Sleep(1) CK13Mhz ENABLE_CK13Mhz SLICER IT Alarm RTC Asynchronous WAKE_UP CLKM WatchDog INTH CK32Khz SPI ULPD MEMINT GSM time B R I D G E TIMER1 TPU RHEA bus ARM7 TSP LPG TIMER2 SIM MCU subchip PWT ARMIO PWL DMA UART IRDA uWIRE uWIRE B R I D G E API UART MODEM LMM M112L00 RHEA bus MCSI RIF INTH DSP subchip CRYPT JTAG Calypso 32KHz QUARTZ 13MHz TCXO External ARM7 Memories

  33. Calypso - Big sleep(2) • Big Sleep - VTCXO ON - ARM clock OFF - TDMA interrupt disabled - GSM Timer interrupt enabled - CLKM, INTH, RTC, ULPD, TPU remain ON - LEAD clock stopped • Big Sleep Wake-up Events - GSM Timer interrupt - ARMIO (keypad) - UART - RTC - All unmasked interrupts - WatchDog timer

  34. Calypso - Deep Sleep(1) CK13Mhz ENABLE_CK13Mhz SLICER IT Alarm RTC Asynchronous WAKE_UP CLKM WatchDog INTH CK32Khz SPI ULPD MEMINT GSM time B R I D G E TIMER1 TPU RHEA bus ARM7 TSP LPG TIMER2 SIM MCU subchip PWT ARMIO PWL DMA UART IRDA uWIRE uWIRE B R I D G E API UART MODEM LMM M112L00 RHEA bus MCSI RIF INTH DSP subchip CRYPT JTAG Calypso 32KHz QUARTZ 13MHz TCXO External ARM7 Memories JQ 19-Jan-1999

  35. Calypso - Deep Sleep(2) • Deep Sleep - VTCXO, ARM clock and all clocks derived from 13 MHz are OFF - TDMA interrupt disabled - GSM Timer interrupt enabled - INTH, RTC, ULPD remain ON - GSM time base on 32 KHz - LEAD clock stopped • Deep Sleep Wake-up Events - GSM Timer interrupt - ARMIO (keypad) - UART - RTC - External IRQ/FIQ (if not masked)

  36. CALYPSO - Serial Port Interface Serial Port Interface * DO NOT COPY *

  37. CALYPSO - SPI: Interface

  38. CALYPSO - SPI: Block Diagram Rhea bus Interface Rhea bus REG_CTRL REG_SET1 REG_SET2 REG_TX_MSB REG_TX_LSB 16 16 clk REG_SR DO clk Clock enable Clock Divider SEQ DI nIRQ REG_RX_MSB REG_RX_LSB REG_STATUS ENi

  39. CALYPSO - SPI : chronograms REG_CTRL write MCU write MCU write REG_TX_MSB register REG_TX (31:16) REG_TX_LSB register REG_TX (15:0) REG_SR register REG_SR(31:0) CLKX_SPI MCUENi d31 d0 MCUDI d31 d0 MCUDO nIRQ nDMA_REQ Status register read REG_STATUS WR or RD =1 REG_RX_MSB register REG_RX(31:16) REG_RX_LSB register REG_RX(15:0) MCU Read MCU Read

  40. CALYPSO - Pins Description of SPI CALYPSO SPI IOTA MCUDI MCUDO TSPACT7 CLKX_SPI MCUEN0 I/O8 MCUEN1 I/O13 MCUEN2 USP UDR UDX UEN

  41. CALYPSO - ARM Interrupts (SPI) IRQ0 IRQ (edge) WatchDog TIMER IRQ1 IRQ (edge) TIMER1 IRQ2 IRQ (edge) TIMER2 IRQ3 FIQ (level) EXT_FIQ, TSP Rx, SIM card insertion/extraction IRQ4 IRQ (edge) TPU frame IRQ5 IRQ (edge) TPU page IRQ6 IRQ (edge) SIM IRQ7 IRQ (level) UART_MODEM or UART_IRDA IRQ8 IRQ (level) Keyboard IRQ9 IRQ (edge) RTC IRQ10 IRQ (level) RTC Alarm, ULPD GSM timer, I2C IRQ11 IRQ (edge) ULPD end of gauging IRQ12 IRQ (level) EXT_IRQ IRQ13 IRQ (edge) SPI IRQ14 IRQ (level) DMA IRQ15 IRQ (edge) API

  42. Calypso - Radio Interface Radio Interface * DO NOT COPY *

  43. Calypso - RIF Connection to RHEA

  44. CALYPSO - Registers of Radio Interface

  45. Calypso - Pins Description of RIF Calypso IOTA RIF BSP BFSX BDX BFSR BDR BFSR BDR BFSX BDX I/O6 BCLKX ARMCLK BCLKR

  46. Calypso - DSP Interrupts (RIF) RSN reset (HW or SW) INT0n RIF receive interrupt INT1n RIF transmit interrupt

  47. CALYPSO - Time Processing Unit Time Processing Unit * DO NOT COPY *

  48. CALYPSO - TPU with TSP TSP TPU SEQUENCER Parallel Interface REG TPU_CTRL ACT[14:0] COMMUNICATION BUFFER Serial Interface Page0 DO Event/Task TDMA TIME-BASE DI Table RHEA BUS CLKX MCU REG OFFSET EN[4:0] Page 1 REG SYNCHRO Event/Task Table IT_FRAME (MCU) IT_GENERATOR IT_PAGE (MCU) IT_DSP (DSP) REG IT_CTRL IT_DSP_PG (DSP) REG IT_STAT

  49. CALYPSO - TPU : micro-instruction set TPU • Micro instructions for time scheduling - start a process at a relative time AT in the frame - load the offset value for the network time OFFSET - load the offset value for the SYNCHRO synchronization time - load the waiting time before execution of WAIT next instruction - stop the sequencer SLEEP • Micro instruction for data processing - write a word (max 8 bits) to a register MOVE

  50. CALYPSO - TPU : General format of micro-instruction INSTRUCTION FOR TIME SCHEDULING Absolute time 0..4999 (qbit GSM step) Instruction code 000 SLEEP 001 AT 010 OFFSET 011 SYNCHRO 101 WAIT b11 b10 b15 b15 b12 b10 b14 b14 b13 b11 b12 b13 b3 b2 b0 b1 b7 b6 b9 b7 b8 b5 b6 b2 b0 b3 b1 b4 b5 b8 b4 b9 INSTRUCTION FOR DATA TRANSFER Data operand Destination address Instruction code 100 MOVE

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