An Extended-Range Ethernet and Clock Distribution Circuit for Distributed Sensor Networks

1. An Extended-Range Ethernet and Clock Distribution Circuit for Distributed Sensor Networks Kael Hanson, Thomas Meures, Yifan Yang Interuniversity Insitute for High Energies (IIHE), Brussels p The ARA collaboration BELGIUM: Univ. Libre de Bruxelles. GERMANY: Univ. of Bonn, Univ. of Wuppertal. JAPAN: Chiba university. TAIWAN: National Taiwan Univ.. UNITED KINGDOM: Univ. College London. USA: Ohio State Univ., Univ. of Delaware, Univ. of Hawaii, Univ. of Kansas, Univ. of Maryland, Univ. of Wisconsin Madison. ARA (THE ASKARYAN RADIO ARRAY ) Motivation : Detecting the GZK-flux • The GZK-mechanism as a “guaranteed” neutrino source: • Very few protons accelerated to UHE within GZK interaction length (most accelerators are further away from earth) • →GZK-mechanism should lead to cutoff in the UHECR spectrum • Cutoff confirmed by the Pierre AUGER Observatory Phys.Lett.B685:239-246, 2010 • Detection method: • Emission of coherent radio waves from neutrino-induced EM-cascades (predicted by Askar’yan, 1962) • Verified at SLAC in 2007Phys. Rev. Lett. 99, 171101, 2007 • Reason: • Radio waves have long attenuation length in ice (~800m), large volumes with small number of antennas ANTENNA (×4)DATA AND CLOCK DISTRIBUTION SYSTEM STATION CONTROLLER ANTENNA DDA ANTENNA ANTENNA ν • The challenge : • Distance:250 meters • Speed: O(10Mbits/s) • Time precision : <50 ps EM cascade Radio-Cerenkov cone SURFACE PROCESS SYSTEM DOWN-HOLE DIGITIZATION SYSTEM Advantages: 4 pairs of differential signals Immunity to common mode noise Standard high speed protocol (10/100/1000Mbps) 37 stations Spacing: 2 km Depth under ice surface: 200 m Surface coverage: ~160 km2 Ice thickness below: ~3000 m Each station: 16 + 4 sub-firn antennas (sensitive between 250 and 800 MHz):8 vertically polarized8 horizontally polarized 4 calibration pulsers (v-pol + h-pol) X surface antennas Disadvantage: Can’t support more than 100 meters (100 Base –T ) Increased signals jitter Standard cat5 twisted pairs clock Driver and PHY Use different pairs in one cat5 solution + data Hpol Quad-slot antenna VSWR < 3 above 300MHz DATA AND CLOCK DISTRIBUTION SYSTEM FPGA FPGA FPGA 20 MHz clock Cable driver Clock Data Data Clock Cable driver PHY PHY Clock conditioner 250 m CAT5 cable Cable equalizer Cable equalizer Clock conditioner RJ45 RJ45 • Performance : • Original clock: yellow • Recovered clock: turquoise Standard cat5 cable (250meters) Future plan Optical data and clock distribution system (2.5Gbps) • Cable driver: • Amplifying the incoming clock to transfer it • 400 ps rise time, 25 ps output jitter • 1 Vpp output • Power consumption: 520 mW • Cable equalizer: • equalization • DC restoration • 750 mVpp output • Power consumption: 255 mW • Clock conditioner: • Loop filtering • Jitter cleaning • Clock distribution • 200 fs output jitter • Power consumption: 578 mW • PHY • 10/100 Mbits/s Ethernet phy,25MHz input clock • In current design: driven by 20MHz clock • 8/80 Mbits/s • Power consumption: 200 mW With synchronized clock, stable connection can be established between two PHY via 250 meters cat5 cable. Precision of period shift between clocks