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Pipeline with Data Forwarding

Solving Data hazards. Pipeline with Data Forwarding. C O N T R O L. M U X. A D D. A D D. 4. Sh L 2. Registers. PC. Instruction Memory. A L U. M U X. Data Memory. Sign Ext. M U X. ALU CTL. M U X. IF. ID/RF. EXE. MEM. WB. Data Hazards.

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Pipeline with Data Forwarding

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  1. Solving Data hazards Pipeline with Data Forwarding

  2. C O N T R O L M U X A D D A D D 4 Sh L 2 Registers PC Instruction Memory A L U M U X Data Memory Sign Ext M U X ALU CTL M U X IF ID/RF EXE MEM WB

  3. Data Hazards • Loop: addi $t0, $t0, 4 • beq $t0, $s1, endLoop • add $t1, $t0, $s0 • add $t2, $t0, $s4 • lw $t3, 0($t1) • lw $t4, 0($t2) • add $t3, $t4, $t3 • sw $t3, 0($t1) • j Loop • endLoop:

  4. C O N T R O L M U X A D D A D D 4 Sh L 2 Registers PC Instruction Memory A L U M U X Data Memory Sign Ext M U X ALU CTL M U X IF ID/RF EXE MEM WB

  5. C O N T R O L M U X A D D A D D 4 Sh L 2 Registers PC Instruction Memory A L U M U X Data Memory Sign Ext M U X ALU CTL M U X IF ID/RF EXE MEM WB

  6. M U X M U X HAZARD M U X CTRL 0 A D D 4 = Reg Instruct Memory PC A L U M U X Data Memory Sign Ext M U X FRWD ALU CTL M U X IF ID/RF EXE MEM WB

  7. C O N T R O L M U X A D D A D D 4 Sh L 2 Registers PC Instruction Memory A L U M U X Data Memory Sign Ext M U X ALU CTL M U X IF ID/RF EXE MEM WB

  8. M U X M U X HAZARD M U X CTRL 0 A D D 4 = Reg Instruct Memory PC A L U M U X Data Memory Sign Ext M U X FRWD Branch forwarding ALU CTL M U X IF ID/RF EXE MEM WB

  9. Unavoidable data hazards • lw data to immediately following instruction • one cycle stall • ALU to immediately following branch • one cycle stall • lw to immediately following branch • two cycle stall • Stalls need circuits to freeze PC and to place 0’s in control line registers

  10. Unavoidable Data Hazards • Loop: addi $t0, $t0, 4 • beq $t0, $s1, endLoop • add $t1, $t0, $s0 • add $t2, $t0, $s4 • lw $t3, 0($t1) • lw $t4, 0($t2) • add $t3, $t4, $t3 • sw $t3, 0($t1) • j Loop • endLoop: Can we reorder code to fix??

  11. Reordered • addi $t0, $t0, 4 • Loop: add $t1, $t0, $s0 • beq $t0, $s1, endLoop • add $t2, $t0, $s4 • lw $t3, 0($t1) • lw $t4, 0($t2) • addi $t0, $t0, 4 • add $t3, $t4, $t3 • sw $t3, 0($t1) • j Loop • endLoop: No longer a problem

  12. M U X M U X HAZARD M U X CTRL 0 A D D 4 = Reg Instruct Memory PC A L U M U X Data Memory Sign Ext M U X FRWD Branch forwarding ALU CTL M U X IF ID/RF EXE MEM WB

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