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Interactions between Processor Design and Memory System Design

Interactions between Processor Design and Memory System Design. David E. Culler CS61CL Nov 25, 2009 Lecture 12. A Processor Centric View. Memory. Processor. Datapath. Control. Fundamental Mem. Design concepts. Caches Virtual memory

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Interactions between Processor Design and Memory System Design

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  1. Interactions between Processor Design and Memory System Design David E. Culler CS61CL Nov 25, 2009 Lecture 12 UCB CS61CL F09 Lec 12

  2. A Processor Centric View Memory Processor Datapath Control UCB CS61CL F09 Lec 10

  3. Fundamental Mem. Design concepts Caches Virtual memory Without these, processing as we know it would not be possible UCB CS61CL F09 Lec 12

  4. A more balanced view Memory Processor “Princeton Architecture” – common instruction and data memory UCB CS61CL F09 Lec 12

  5. A more balanced view Instruction Memory Data Memory Processor “Harvard Architecture” – separate instruction and data memory UCB CS61CL F09 Lec 12

  6. Or really Memory Processor Memory systems are extremely sophisticated Parallelism, caching, controllers, protocols, … UCB CS61CL F09 Lec 12

  7. Pipeline design: I-miss handling Dmem imem °°° A + IR IR_ex IR_mem IR_wb PC B Ci Insert a no-op “bubble” till i-fetch completes UCB CS61CL F09 Lec 10

  8. Pipeline Design: D-miss Dmem imem °°° A + IR IR_ex IR_mem IR_wb PC B Ci Stall entire pipeline behind mem stage for data miss penalty Bubble the remainder (WB) UCB CS61CL F09 Lec 10

  9. Performance “Iron Triangle” CPI Cycle Time Inst. Count • Execution Time = Seconds / Program = Seconds X Cycles X Instructions Cycle Instruction Program = CycleTime X CPI X Inst.Count • What primarily determines… • Cycle Time? • Instruction Count? • CPI ? UCB CS61CL F09 Lec 12

  10. Bringing Cache into the Picture • Recall MAT = Timehit + Pmiss * Penaltymiss • Timehit < Cycle Time • Penaltymiss = Pipeline Stalls/Bubbles during miss • Ideal CPI is CPI with perfect memory system • CPI = Ideal_CPI + Pmiss* Penaltymiss UCB CS61CL F09 Lec 12

  11. Example • Instruction Mix: • 50% arith, 30% load/store, 20% jumps/branches • Pipeline hazards • Ideal CPI = 1.2 • Cache behavior • 0.2% instruction miss rate (99.8% hit rate) • 3% data miss rate (97% hit rate) • 100 cycle miss penalty • Without Cache: CPI = 1.2 + 100 + 0.30 x 100 = 131.2 • processor pipeline is 0.7% utilized !!!! • Cache: CPI = 1.2 + 1 x 0.002 x 100 + 0.30 x 0.03 x 100 = 1.2 + 0.2 + 0.9 = 2.3 on average ~half the time is spent waiting for mem. UCB CS61CL F09 Lec 12

  12. Administration • Midterm II results • Max: 99 Mean: 75.2 (without bonus) • Max: 105.5 Mean 77 • HW 8 due 12/7 midnight • Project 4 due 12/9 midnight • Review Week • review in Tu/W lab + optional threads lab • review in lecture • Final Exam: Dec 15 12:30 -3:30 UCB CS61CL F09 Lec 12

  13. Virtual Memory Each Program runs in its own Virtual Address Space (VAS) Distinct from the Physical Address Space (PAS) of the machine Hardware transparently maps the Virtual Address Spaces onto physical resources Only a small fraction of the VAS’s in physical memory at any time! UCB CS61CL F09 Lec 12

  14. Timesharing, MultiProcessing, Multitasking UCB CS61CL F09 Lec 12

  15. Multiple Process Address Spaces in Mem 00000000 Physical Memory 00000000 00FD0000 FFFFFFFF UCB CS61CL F09 Lec 12

  16. With Virtual Memory 00000 00000000 Physical Memory 00FD0000 FFFFF FFFFFFFF UCB CS61CL F09 Lec 12

  17. A Processor Supporting Virtual Memory • Is able to access a Page Table to translate Virtual Page Number => Physical Frame • on EVERY memory reference • Page Table lives in memory • How many memory accesses per instruction? • Instruction Fetch VA Translation • PF = Mem[ PTbase + PC_page] • Fetch the Actual Instructions • IR = Mem[ PF + PC_offset] • Load/Store VA Translation • PF = Mem[ PTbase + (R[rs]+Sx)_page ] • Load/Store the actual location • R[rt] = Mem[ PF + (R[rs]+Sx)_offset ] • How many cache accesses? UCB CS61CL F09 Lec 12

  18. TLB ???? Translation Lookaside Buffer is a specialized cache for the page table It was invented (by Sir Maurice Wilkes) to make virtual memory possible He then realized it could be used to make all memory accesses faster. Should TLBs and caches be different? UCB CS61CL F09 Lec 12

  19. What must happens in the processor on a Page Fault? • It could happen in instruction fetch, LW or SW • The translation fails • The actual page is out on disk • 10 ms @ 3 GHz => 30 Million cycles to access it! • We need to run a special program (The Operating System) to go and get it • allocate a frame in memory • read the page from disk • seek • transfer, … • update the page table • But we are in the middle of an instruction… UCB CS61CL F09 Lec 12

  20. Page Fault Dmem imem °°° A + IR IR_ex IR_mem IR_wb PC B Ci Cannot just stall the pipeline Must “trap” the current instruction Put it aside and start executing other (OS) instructions UCB CS61CL F09 Lec 10

  21. More Key Concepts • Exception: unprogrammed transfer of control • Interrupt • asynchronous • occurs between instructions • used for efficient I/O • Fault • synchronous • occurs within an instruction • Preserve state associated with trap in special registers • EPC + BADVad + Cause in MIPS • Modify PC register to be exception handler • PC := trapHandlerAddr UCB CS61CL F09 Lec 12

  22. What information must be recorded on a page fault? • The PC of offending instruction • The offending address • other cause-related info UCB CS61CL F09 Lec 12

  23. Page Fault in Action Physical Memory Disk 07 0000 page 0040 Page Table 0040 v: 07 Program Virtual Address Space PTB Regs TLB 0040 => 07 Processor PC 0040 0010 IR badVA ePC UCB CS61CL F09 Lec 12

  24. Inst Fetch: VA 0040xxxx => PA 07xxxx Physical Memory Disk 07 0000 page 0040 Page Table 0040 v: 07 Program Virtual Address Space PTB Regs TLB 0040 => 07 Processor PC 0040 0010 IR badVA ePC UCB CS61CL F09 Lec 12

  25. Inst Fetch: mem[07 0010] => IR Physical Memory Disk 07 0000 page 0040 Page Table 0040 v: 07 Program Virtual Address Space PTB Regs TLB 0040 => 07 Processor lw $3 20($4) PC 0040 0010 IR badVA ePC UCB CS61CL F09 Lec 12

  26. Exec: EA = 0053 1000 + 20 Physical Memory Disk 07 0000 page 0040 Page Table 0040 v: 07 Program Virtual Address Space PTB Regs TLB 0040 => 07 0053 1000 Processor lw $3 20($4) PC 0040 0010 IR badVA ePC UCB CS61CL F09 Lec 12

  27. Exec: VA 00531020 => ??? TLB miss Physical Memory Disk 07 0000 page 0040 Page Table 0040 v: 07 Program Virtual Address Space PTB Regs TLB 0040 => 07 0053 1000 Processor lw $3 20($4) PC 0040 0010 IR badVA ePC UCB CS61CL F09 Lec 12

  28. Exec: PT lookup(0053) => ??? Fault Physical Memory Disk 07 0000 page 0040 Page Table 0053 v: 07 N: Program Virtual Address Space PTB Regs TLB 0040 => 07 0053 1000 Processor lw $3 20($4) PC 0040 0010 IR badVA ePC UCB CS61CL F09 Lec 12

  29. Exec: Trap to OS Page Fault Handler Physical Memory Disk 07 0000 page 0040 Page Table 0053 v: 07 N: Program Virtual Address Space PTB Regs TLB 0040 => 07 0053 1000 Processor 00001 FF00 lw $3 20($4) PC 0040 0010 IR badVA 0040 0010 0053 1020 ePC UCB CS61CL F09 Lec 12

  30. Fetch and execute OS instructions OS page Physical Memory Disk 07 0000 page 0040 Page Table 0053 v: 07 N: Program Virtual Address Space PTB Regs TLB 0040 => 07 0053 1000 Processor 00001 FF00 j flt_hndlr PC 0040 0010 IR badVA 0040 0010 0053 1020 ePC UCB CS61CL F09 Lec 12

  31. Fetch and execute OS instructions OS page Physical Memory Disk 07 0000 page 0040 Page Table 0053 v: 07 N: Program Virtual Address Space PTB Regs TLB 0040 => 07 0053 1000 Processor 000YY xxxx jxzyxzyxz PC 0040 0010 IR badVA 0040 0010 0053 1020 ePC UCB CS61CL F09 Lec 12

  32. Load page from Disk to Memory OS page Physical Memory Disk 07 0000 page 0040 page 0053 Page Table 0053 v: 07 N: Program Virtual Address Space PTB Regs TLB 0040 => 07 0053 1000 Processor 00001 FF00 j flt_hndlr PC 0040 0010 IR badVA 0040 0010 0053 1020 ePC UCB CS61CL F09 Lec 12

  33. Update Page Table OS page Physical Memory Disk 07 0000 page 0040 14 0000 page 0053 Page Table 0053 v: 07 v: 14 Program Virtual Address Space PTB Regs TLB 0040 => 07 0053 1000 Processor 00001 FF00 j flt_hndlr PC 0040 0010 IR badVA 0040 0010 0053 1020 ePC UCB CS61CL F09 Lec 12

  34. ReturnFromException (RFE) OS page Physical Memory Disk 07 0000 page 0040 14 0000 page 0053 Page Table 0053 v: 07 v: 14 Program Virtual Address Space PTB Regs TLB 0040 => 07 0053 1000 Processor lw $3 20($4) PC 0040 0010 IR badVA 0040 0010 ePC UCB CS61CL F09 Lec 12

  35. Exec: TLB Miss, PT lookup OS page Physical Memory Disk 07 0000 page 0040 14 0000 page 0053 Page Table 0053 v: 07 v: 14 Program Virtual Address Space PTB Regs TLB 0040 => 07 0053 1000 0053 => 07 Processor lw $3 20($4) PC 0040 0010 IR badVA ePC UCB CS61CL F09 Lec 12

  36. Exec: Read physical address OS page Physical Memory Disk 07 0000 page 0040 14 0000 page 0053 Page Table 0053 v: 07 v: 14 Program Virtual Address Space PTB Regs TLB 432 0040 => 07 0053 1000 0053 => 07 Processor lw $3 20($4) PC 0040 0010 IR badVA ePC UCB CS61CL F09 Lec 12

  37. Paging the Page Table? 264 byte virtual address space 214 byte pages (16 kB) => 250 page table entries Large address spaces are used sparsely UCB CS61CL F09 Lec 12

  38. Summary Caches are essential to performance Virtual Address translation permits modern operating systems and applications Requires caching Also requires special processor hardware support Also requires operating system support Works as long as page faults are rare Next Time: Andy lectures on “What’s an OS” UCB CS61CL F09 Lec 12

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