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Total Ionizing Dose Effects in Bulk Technologies and Devices. Hugh Barnaby, Jie Chen, Ivan Sanchez Department of Electrical Engineering Ira A. Fulton School of Engineering Arizona State University. Outline. Overview of ASU tasks Total ionizing dose defect models Device TID response
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Total Ionizing Dose Effects in Bulk Technologies and Devices Hugh Barnaby, Jie Chen, Ivan Sanchez Department of Electrical Engineering Ira A. Fulton School of Engineering Arizona State University
Outline • Overview of ASU tasks • Total ionizing dose defect models • Device TID response • Drain-to-source leakage • Inter-device leakage • Analysis of defect buildup across oxide structure and between technologies • Other work
ASU task • Characterize and model TID effects in modern devices, primarily CMOS transistors • Technologies: deep sub-micron bulk CMOS, and silicon on insulator, general isolations
ASU task • Characterize and model TID effects in modern devices, primarily CMOS transistors • Technologies: deep sub-micron bulk CMOS, and silicon on insulator, general isolations In Year 1, we have primarily focused ondeep-sub-micron bulk CMOS and generalisolation technologies.
Primary TID Threat TID defect build-up in the “thick” shallow trench isolation (STI) Defects • Not - oxide trapped charge (E’ ) • Nit – interface traps (Pb) Both Nit and Not are related to holesgenerated and/or hydrogen present inoxide first orderassumption Not, Nita tox
Model for Not buildup After Fleetwood et al. TNS 1994 Model Parameters D - total dose [rad] kg - 8.1 x 1012 [ehp/radcm3] fy - field dependent hole yield [hole/ehp] fot - trapping efficiency [trapped hole/hole] tox - oxide thickness [cm]
Hole trapping processes - surviving hole (p) + - hole trap (NT) - trapped hole (Not) + fp - hole flux area = s(e)
Simple analytical model (Not) (steady state) (fp > 0 for all x) fot D (No saturation or annealingand traps at interface) After Rashkeev et al. TNS 2002
Model for Nit buildup After Rashkeev et al. TNS 2002 Model Parameters D - total dose [rad] kg - 8.1 x 1012 [ehp/radcm3] fy - field dependent hole yield [hole/ehp] fDH - hole, D’H reaction efficiency [H+/hole] fit - H+, SiH de-passivation efficiency [interface trap/H+] tox - oxide thickness [cm]
De-passivation processes - hydrogen defect (D’H) - protons H+ - Si-H (NSiH) H - dangling bond (Nit) - proton flux fH area = sit
De-passivation processes (steady state) (fH > 0 for all x) D fit (No saturation or annealingand traps at interface) After Rashkeev et al. TNS 2002
Leakage paths Defect build-up in STI creates leakage paths in CMOS ICs. NMOS Drain-to-Source 1 NMOS D/S to NMOS S/D 2 3 NMOS D/S to NWELL 3 2 1 2 and 3 are inter-device leakage CMOS inverters
NMOS drain-to-source leakage Increasingtotal dose
Parasitic leakage model • Parasitic “edge” device modeled as MOSFET operating in parallel with “as drawn” FET. • “Effective” parameters for “edge” device are extracted from data.
Extracting electrical characteristics ID“edge”(post)≈ IDtotal(post) – IDtotal(pre) IDtotal(post) • Two assumptions: • IDtotal(pre) ≈ ID“as-drawn”(pre) • ID“as-drawn”(post) ≈ ID“as-drawn”(pre) ID“edge”(post) IDtotal(pre)
“Edge” Capacitor Prior to radiation exposure, the MOS capacitor of the “edge” device has small dimensions, W and tox a tox-eff Weff + + + STI +
“Edge” Capacitor Upon radiation exposure, the “edge capacitor is degradedand the dimensions enlarged. a tox-eff Weff + + + + STI + + a tox-eff Weff + + + + + + Increasingtotal dose STI +
“Edge” Capacitor Increased defect buildup in theSTI sidewall leads to further increases in W and tox, until inherent limitations are met. a tox-eff Weff + + + + STI + + a tox-eff Weff + + + + + + Increasingtotal dose + + + + STI + + + + + + + a tox-eff + + Weff + + + + + + + + + STI +
2D simulations Simulations show how increased Not along sidewall increases the width of the channel and the capacitor thickness Weff Weff Weff Not = 2×1012 cm-2 Not = 5×1012 cm-2 Not = 7×1012 cm-2
New Test Structure Devices designed by Faccio and fabricated at STMicro enable measurements on sidewall capacitor. • 90 um Pre-rad • 1.3 um overlap
Parameter extraction • Weff increases withTID (increased strong -inv current) • Not and Nit increase with TID (shift in threshold voltage) • Nitandtox increasewith TID (reducedsubthreshold slope) • Not increasewith TID (shifts inmidgap voltages)
Simultaneous equations 1. 2. 3. 4. Solving simultaneouslyenables extraction of parameters and defectlevels at each TID value
Parameters and sidewall defects Parameters Defects
Inter-device leakage n+ D/S to n-well n+ D/S to n+ D/S Charge build-upin STI base
Field oxide transistors n p - - well well Metal 1 n-well n+ D/S n+ n+ + + + + STI - n+ D/S Metal 1 noise floor n-well 130 nm bulk CMOS
Field oxide capacitors Single cell 1500 Single Cell FOXCAPs in parallel gate area of individual cell ~ 7.4 μm x 11.4 μm 130 nm data
Defect build-up in STI base • Defect build-up is: • Greater for higher oxidefields (consistent w/ fy) • Linear with dose(no saturation … yet)
Comparison to other isolation technologies (Not) *data taken after 20 krad(SiO2) exposures **radiation bias is 0V for all devices
Sidewall vs. Base Comparison (Not) Indicates saturation in defect buildup
Other Work • Separation of switch state defects in thick isolationoxides using frequency dependent charge pumping • Packaging issues
Gate sweep data Nss Nss Increased current is caused by switching state buildup (Nss) whichis composed of both interface and border traps
Separation of Switching States Indicates border traps
Packaging Issues • Recent testing showed 3x increase in Nit in GLPNP devices packaged with sealed gold plated kovar lids than packages with taped-on lids.
It’s a hydrogen problem • As sealed lid is removed, H2 moves quickly out of the package and a concentration gradient is established for the remaining H2 in the oxide to diffuse out, thus reducing Nit generation.
Another time dependent process Results shows time dependence of Nit build-up related hydrogen out diffusion … we are working on the rate equations for this