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Final Presentation Part-A

Final Presentation Part-A. Infrastructure design & implementation of MIPS processors for students lab based on Bluespec HDL. Students: Danny Hofshi, Shai Shachrur Supervisor: Mony Orbach. Winter 2012. Reminder. FPGA. C++. Bluespec Scemi. Bluespec HDL.

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Final Presentation Part-A

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  1. Final PresentationPart-A Infrastructure design & implementation of MIPS processors for students lab based on Bluespec HDL Students: Danny Hofshi, Shai Shachrur Supervisor: MonyOrbach Winter 2012

  2. Reminder FPGA C++ BluespecScemi Bluespec HDL

  3. Project Goals (from characteristic presentation) • Part A: Creating the Laboratory working environment. • Hardware environment – RTL , interface to outer world ( pci - express ), Xilinx utilities. • Software environment – simulation of a MIPS processor on the above RTL using simplified commands, the same environment will be used for emulation and simulation.

  4. Lab staff Danny & Shai Project Characterization performance questions Program for testing Multi cycle MIPS hardware Test, Sync & Conclusions We are here Part A Adjusting the experiment flow Designing the MIPS improvements Running a pilot group Part B

  5. What has been done • Hardware infrastructure

  6. Hardware Linux Environment PCIe cable Virtex 5 FPGA

  7. What has been done • RTL Design

  8. MIPS Design • BlueSpec • S C E M I • - PCIe • Clk control Communicating with a c++ environment using generic interface BlueSpec Xilinx BRAM Co-Processor Xilinx BRAM

  9. The MIPS state machine

  10. What has been done • Software environment

  11. Control interface • Ability to Put & get data from the instruction memory. • Ability to Put & get data from the data memory. • Ability to control the MIPS operation (Co-processor) - stop - load PC, start & wait for interrupt - load PC & start for a specific number of cycles • Retrieve performances (Co-processor). • Number of clock cycles. • Number of Instructions.

  12. SCEMI

  13. Compiler • Perl Script compiler – translate assembler code to our specific SCEM interface. 604569602 0 0 1 0 604635138 4 4 1 0 1952289 8 8 1 0 2 8 86402048 12 12 1 0 1082130432 16 16 1 0 0 1 1 1 2 2 0 0 1 2 1 0 0 1 2 addi $t1 $zero 2 addi $t2 $zero 2 add $t3 $t1 $t2 sw $t3 $zero 0 stop Processor commands Stop command will generate an interrupt Load PC Set PC Start

  14. User work Flow Write Assembler Code & Data memory Type executable command Receive performances and data Communication module C++ MIPS addi $t1 $zero 2 addi $t2 $zero 2 add $t3 $t1 $t2 sw $t3 $zero 0 stop Compiler Data received 604569602 0 0 1 0 604635138 4 4 1 0 1952289 8 8 1 0 2 8 86402048 12 12 1 0 1082130432 16 16 1 0 0 1 1 1 2 2 0 0 1 2 1 0 0 1 2

  15. On the PC

  16. Lab staff Danny & Shai Project Characterization performance questions Program for testing Multi cycle MIPS hardware Test, Sync & Conclusions We are here Part A Adjusting the experiment flow Designing the MIPS improvements Running a pilot group Part B

  17. Test program The Bubble sort Assembler code: // size of array addi $s0 $zero 64 // address counter addi $s1 $zero 0 // swap indicator start : addi $s2 $zero 0 start_in_iteration : lw $t0 $s1 0 lw $t1 $s1 4 // $t0=1 if we need to swap, $t0=0 else slt $t3 $t1 $t0 beq $t3 $zero no_swap sw $t0 $s1 4 sw $t1 $s1 0 // set swap indicator addi $s2 $zero 1 no_swap : beq $s1 $s0 end_iteration addi $s1 $s1 4 beq $zero $zero start_in_iteration end_iteration : beq $s2 $zero stop_sort addi $s1 $zero 0 addi $s0 $s0 -4 beq $s0 $zero stop_sort beq $zero $zero start

  18. Run The program Run on the CPU. Typing the command line to compile and run the above code [s03992455@diglabl2 fpga]$ perlparser.pl -source bubble_sort.S -end -meminit mem_init.txt Starting to parse code  ********* Running command_file.txt ************ (Writing Data to the I-MEM) Loading data to I-mem: 605028416 0 0 1 0 Loading data to I-mem: 605093888 4 4 1 0 Loading data to I-mem: 605159424 8 8 1 0 Loading data to I-mem: 2384986112 12 12 1 0 Loading data to I-mem: 2385051652 16 16 1 0 Loading data to I-mem: 19421226 20 20 1 0 Loading data to I-mem: 291504131 24 24 1 0 Loading data to I-mem: 2921857028 28 28 1 0 Loading data to I-mem: 2921922560 32 32 1 0 Loading data to I-mem: 605159425 36 36 1 0 Loading data to I-mem: 305135618 40 40 1 0 Loading data to I-mem: 640745476 44 44 1 0 Loading data to I-mem: 268500982 48 48 1 0 Loading data to I-mem: 306184196 52 52 1 0 Loading data to I-mem: 605093888 56 56 1 0 Loading data to I-mem: 638648316 60 60 1 0 Loading data to I-mem: 301989889 64 64 1 0 Loading data to I-mem: 268500976 68 68 1 0 Loading data to I-mem: 1082130432 72 72 1 0 Loading to arg register 0 1 1 1 2  (Loading the start value of the MIPS Program counter) Load PC from arg register2 0 0 1 2 (Applying the start value to the PC) Start CPU 1 0 0 1 2 (Starting the run on the MIPS) ####### Program run on CPU finished ####### (Receiving an interrupt from the PC) SceMi Service thread finished! SceMi Service thread finished!

  19. Results  ********* inquiring check_mem.txt ************ (Reading the performance counters sort DATA) requesting number of cycles  (Sending a data request to the Co-processor) number of clock cycles is 591 number of instructions is 122 {data 32'h00000011 resp_type 4'h1 resp_addr 32'h00000000} {data 32'h00000014 resp_type 4'h1 resp_addr 32'h00000004} {data 32'h00000015 resp_type 4'h1 resp_addr 32'h00000008} {data 32'h00000037 resp_type 4'h1 resp_addr 32'h0000000c} {data 32'h0000003c resp_type 4'h1 resp_addr 32'h00000010} {data 32'h0000003d resp_type 4'h1 resp_addr 32'h00000014} {data 32'h0000003d resp_type 4'h1 resp_addr 32'h00000018} {data 32'h00000045 resp_type 4'h1 resp_addr 32'h0000001c} {data 32'h00000047 resp_type 4'h1 resp_addr 32'h00000020} {data 32'h0000004a resp_type 4'h1 resp_addr 32'h00000024} {data 32'h0000004d resp_type 4'h1 resp_addr 32'h00000028} {data 32'h00000050 resp_type 4'h1 resp_addr 32'h0000002c} {data 32'h00000053 resp_type 4'h1 resp_addr 32'h00000030} {data 32'h00000058 resp_type 4'h1 resp_addr 32'h00000034} {data 32'h00000059 resp_type 4'h1 resp_addr 32'h00000038} {data 32'h0000005d resp_type 4'h1 resp_addr 32'h0000003c} {data 32'h00000060 resp_type 4'h1 resp_addr 32'h00000040} {data 32'h00000061 resp_type 4'h1 resp_addr 32'h00000044} Finished parsing 591 Cycles 122 Instructions 4.844 Cycles per instruction

  20. Remarks • We can also run in simulation mode for RTL debug. • A full verification on the whole MIPS command set was made.

  21. We implement Meow prediction ? Discussion

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