Presenter: PCLee 2012.08.27

1. Paper presentation:Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCsHo Fai Ko, Adam B. Kinsman and Nicola NicoliciDepartment of Electrical and Computer EngineeringMcMaster University, Hamilton, ON L8S 4K1, Canada Presenter: PCLee 2012.08.27

2. Abstract • Post-silicon validation is used to identify design errors in silicon. Its main limitation is real-time observabilityof the circuit’s internal nodes. In this paper, we introduce a novel design-for-debug architecture which automatically allocates distributed trace buffers to handle debug data acquisition requests from multiple sources located in different cores. Using resource-efficient and intelligent control placed on-chip, we show how real-time observability can be improved, thus helping bridge the gap between pre-silicon verification and post-silicon validation for SOC designs.

3. Introduction • What’s the problem: • Pre-silicon verification is insufficient in eliminating error because the complex SOC design. • The previous DFD architecture is not flexible for each design. • The proposed method: • Trace buffer-based debug. • Real-time observabilityin multi-core design. • DFD architecture on distributed embedded logic analysis.

4. Related work [20] Scan-based debug Real-time in not possible cause CUD has to stop Trace buffer-based debug [16] centralized trace buffer [2][11][21] Trigger units [3][7] compression technique [10]data restoration technique Not simultaneous [1]distributed trigger unit [6]assertion checker [13]cross trigger [14] Multi trace buffers 1.multi-core debug 2.high-speed trace ports THIS PAPER

5. Challenges • When there are multiple trigger events occurring simultaneously, how to choose trace buffers to sample data from different data sources? • When some of the trace buffers are already occupied, is it necessary to reallocate the trace buffers when a new trigger event from a different data source occurs? • How to allocate trace buffers when the number of sample requests is more than the number of available trace buffers? • How to allocate trace buffers for data sampling before knowing when trigger events from multiple data sources will happen? • How to decide which trace buffers to offload first when multiple trace buffers are idle? • How to balance the sampled data among trace buffers such that more trace buffers will have available space for fulfilling upcoming data acquisition requests? • In the case when debug experiments are repeatable, can the controller be reprogrammed to acquire different sets of debug data during each rerun of the experiment?

6. The proposed DFD architecutre

7. Allocation unit Trace buffer control unit update the status registers for controlling the read/write operations of the trace buffers. Decide the priority of each segment data in trace buffer Decide where the debug data should be allocated. Information about data smpling before trigger

8. Handling of simultaneous, overlapping, and overflow sample requests (Features A-C) Queue FSM decides priority Over-writing some segment of 3

9. Data sampling before trigger (Feature D) • Configure two control register first • Window size: how big does the debugging data we need • Window position: starting address of the debugging data Continuously instead data Continuously instead data

10. Out-of-order data offloading (Feature E) Queue FSM decide priority of offloading

11. Programmable priority (Feature G) Queue FSM is reprogrammable, let us change the priority

12. Experiment environment

13. Experimental result

14. Conclusion • Paper conclusion: • This paper introduced a novel DFD architecture for complex multi-core designs. • My conclusion: • They consider many scenarios to solve the problems in multi-core debug. • The reconfigurable mechanism for FSM makes debugging more flexible. • The implementation and application are advancement.