Machine Architecture Fetch – Decode - Execute

1. Machine ArchitectureFetch – Decode - Execute

2. Stored Program Concept • Modern computers use the stored program concept. • The stored program concept is that: • machine code instructions are stored in main memory, • these are fetched and executed serially, • by a processor that performs arithmetic and logical operations. • The concept was introduced by John von Neumann. • Previously, “programs” were entered into a computer by techniques such as setting switches and plugging patch leads into panels. • The concept can be seen earlier in Alan Turing’s development of the Universal Turing Machine.

3. Colossus 1943

4. The Fetch-Execute Cycle The Fetch-Execute cycle is the basic operation cycle of a computer. The cycle is repeated over and over again from the moment a computer is turned on until it is turned off. Each time that the cycle is iterated, a single machine code instruction if fetched from main memory, decoded and executed. The result (output) of an instruction is usually stored into a general purpose register but could also be written back to main memory.

5. F-E Cycle Stages The Fetch-Execute cycle has three stages: Fetch: The instruction to execute is retrieved from the main memory. Decode: The op-code part of the instruction is examined to determine which parts of the CPU must be used to carry out the instruction. Execute: The appropriate hardware components of the CPU are used to carry out the instruction.

6. F-E Cycle Registers • The Fetch-Execute cycle makes use of some specific purpose registers on the processor: • Program Counter (PC): Stores the address in main memory of the next instruction to execute. • Memory Address Register (MAR): Stores the address in main memory of the location that the processor is currently reading data from or writing data to. • Memory Buffer Register (MBR): Temporarily stores the word of data that is currently being transferred between the processor and the main memory. • Current Instruction Register (CIR): Stores the instruction that is currently being executed by the processor whilst it is decoded and executed.

7. F-E Cycle Notation The steps involved in the Fetch-Execute cycle are often described in register transfer notation. This has the format: Register / Storage Location  Value e.g. MAR  [PC] means that the contents of the Program Counter are copied into the Memory Address Register The symbols [] are used to indicate the contents or a register or storage location.

8. F-E Cycle Animation (1) The animation on the next slide shows one iteration of the fetch-execute cycle, to carry out the instruction stored in memory location 104. The animation focuses in most detail on the fetch stage of the cycle as this stage is the same for all instructions.

9. F-E Cycle Animation (2) 1 MAR  [PC] (Contents of Program Counter transferred to MAR) (a) PC  [PC] + 1 (Increment contents of Program Counter) (b) MBR  [Memory]addressed (Contents of addressed memory location loaded into MBR) 2 Simultaneous • Memory address transferred along address bus to main memory. CIR  [MBR] (Transfer contents of Memory Buffer Register into Current Instruction Register) • Contents of addressed location looked up in main memory. 3 • Looked up value transferred to processor along data bus. Processor Main Memory Address Content 100 01110101101 11010101102 00101000103 11011001104 10000101105 10101101106 01001101 PC MAR 4 Address Bus Decode instruction +1 105 104 104 104 5 CIR MBR Data Bus Execute instruction 104 10000101 10000101 10000101 10000101

10. F-E Cycle Decode Stage (1) instruction 10000101 1000 0101 op-code operand During the decode stage, the control unit splits the instruction in the CIR into two parts: Op-code: The binary pattern which identifies the instruction to be carried out e.g. add, or, branch. Operand: The data that the instruction will operate on.

11. F-E Cycle Decode Stage (2) The operand could be a number such as 5, which the instruction should use directly. Alternatively it might be the address in main memory where the data to use is stored. How to interpret the operand will depend upon the addressing mode that the instruction is using. Instructions may have zero, one or more operands.

12. F-E Cycle Execute Stage (1) What happens in the execute stage of the cycle is determined by the op-code of the instruction that is being executed. The op-code will determine which circuitry within the processor should be used to carry out the instruction. Temporary results and the final result of executing instructions are usually stored in registers instead of main memory as registers can be accessed much more quickly. Modern computers have many general purpose registers, but it can be convenient to think of a simplified model of a computer with just one general purpose register, known as the accumulator.

13. F-E Cycle Execute Stage (2) The example below shows the execute stage for an ADD instruction that adds the value in a specified memory location onto the current value in the accumulator register, storing the result in the accumulator.

14. F-E Cycle Execute Stage (3) After an instruction has been executed, the contents of a special purpose register known as the status register are updated. Each bit of the status register is known as a flag and has a specific purpose. Some example status register bits are: The status register stores information about the result of previous operations as these may affect future operations.