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Lab1 goal

Lab1 goal. 繪製有關 Schematic 的練習 學會如何利用 layout 畫出 logic gate 利用 DRC check 來找出錯誤. Flow for environment. Step1: 準備好相關的 technology files Step2:check 工作站 cadence 的版本,並設定 cds.lib 檔案 Step3: 啟動 cadence,% icfb&. Flow for schematic. Step1: 建立 library, 之後在建立 cell Step2: 之後在建立 schematic view, 並且畫出

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Lab1 goal

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  1. Lab1 goal • 繪製有關Schematic的練習 • 學會如何利用layout畫出logic gate • 利用DRC check來找出錯誤

  2. Flow for environment • Step1:準備好相關的technology files • Step2:check工作站cadence的版本,並設定cds.lib檔案 • Step3:啟動cadence,% icfb&

  3. Flow for schematic • Step1:建立library,之後在建立cell • Step2:之後在建立schematic view,並且畫出 • Step3:check無誤後建立symbol view

  4. Flow for layout • Step1:在同一個library下,建立layout view • Step2:開始畫layout • Step3:畫好後再經過DRC verification • Step4:check無誤後再extract建立extract view • Step5:利用CIW,CDL out出extract的netlist檔

  5. Handout • 下面是一些簡單的範例 • Ex: 2-input NOR-gate的schematic跟layout • Ex: 2-input NAND-gate的schematic跟layout • Ps:注意pin name

  6. 2-NOR gate schematic

  7. 2-NOR gate layout

  8. 2-NAND gate schematic

  9. 2-NAND gate layout

  10. Hw1 • 畫出3-input NOR gate and 3-input NAND gate 的layout及schematic的diagram • 注意所有的schemtaic都必須check過無誤 • 所有的layout都必須經過DRC check驗證

  11. Hw1 cont. • 請將extracted做 cdl-out轉出netlist file • print out layout diagram and schematic diagram • layout must pass online DRC check. • 若需全部full custom 實驗操作手冊,請到331找Lab1助教影印。

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