EE878 Term Project Proposal

1. IP RT-level Verilog Model Document based on VSIA automation  New requirement for document the RT-level IP DataBase IP Design IP Documentation IP Document IP User IP Vendor Reuse System EE878 Term Project Proposal  What To Do?  Why To Do? Specification Generation of RT-level Verilog IP

2.  Method 1 - Utilizing the Information extractable from IP itself Document  Specification  block diagram  timing diagram . . . . (based on VSIA) IP RT-level Verilog model Verilog parser Internal Data Structure Extract Wanted Info DEVS based EE878 Term Project Proposal  How To Do?  Method 2 - Utilizing the meta comment  Put information on comment section ex.) synthesis Specification Generation of RT-level Verilog IP