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ASIC at SMU

ASIC at SMU. A brief history, and lessons to be learned. Two recent designs, the technical aspect: A LC based Phase Locked Loop (PLL) A 16:1 serializer at 5 Gb/s. Phase I, with EE. 2004: decision on “ASIC for the LHC upgrade”.

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ASIC at SMU

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  1. ASIC at SMU • A brief history, and lessons to be learned. • Two recent designs, the technical aspect: • A LC based Phase Locked Loop (PLL) • A 16:1 serializer at 5 Gb/s

  2. Phase I, with EE • 2004: decision on “ASIC for the LHC upgrade”. • 2004/2005: collaboration with SMU EE department, proposal to US-ATLAS about development of 10 Gb/p serializer using an SOS technology, funded at ~$160k/yr for 3 yrs. • 2005/2006: irradiation tests on a laser driver about the SOS technology and concluded that a dedicated test chip would be needed to understand at transistor level this issue. Test chip: 96 transistors w/ different size and layout. Shift registers, ring oscillators. VCO. Resistors.

  3. Phase I, with EE • The design environment was from the EE department which has one staff for Cadence and one student for the foundry design kit. • 2006/2007: design the first serializer chip (LOC1) with one EE prof. + two graduate students. • 2007: function tests of LOC1 (Datao) and found that it fails the requirement of a 2.5 Gb/p serializer. Reason: no deep understanding of the circuits, no thorough simulation of the design; no collaborative efforts.

  4. Phase I, with EE An LC based PLL was also implemented

  5. Phase II, on our own • 2007/2008: decision to terminate the collaboration with the EE department. • 2008/2009: set up the design environment in Physics. About 25% of the computer admin’s time on a server (8 CPUs, 64 GB memory) and 10% of Datao’s time on the design kit, with a lot of help from an engineer from the foundry. Foundry’s willingness to help is very important. • Datao took one semester course on IC design. Prior to this, Tiankuan took one semester course as well. • 2008 4Q: start the design of LOC2, a 5 Gb/p serializer. Will report in detail later. • Painfully slow progress due to new to the field, and no critical mass in the lab: Datao had no one to discuss on a day-to-day basis. I facilitated Datao with experts from U. of Chicago, TI, IPHC, CERN and Upenn.

  6. Phase II, on our own • 2009 1Q: Tiankuan jumped in on a 5 GHz LC based PLL. • 2009, until August: with tremendous help from Fukun, Christine (IPHC Strasbourg) and Paulo (CERN), and with a lot of creative work from a team of Datao, Tiankuan, a graduate student (Qinghua) and myself, we completed the designs for LOC2 and the LCPLL. Both will be reported later. • 2010/2011: test of LOC2 and the LCPLL, design of LOC3. Move to IBM 90 nm technology. LOC2, LCPLL and other testing structures: varactor, RAM, CML driver

  7. Lessons Learned • ASIC is do-able with efforts and moderate resource. • It is possible to take off within 18 months, if no mistakes in decision making process. • Help from experts is a big booster to take off. The fastest way is to learn from experts in a project. • It needs a dedicated team with a critical mass to achieve necessary efficiency. • Choose a technology and foundry service carefully. Foundry’s support becomes vital if special needs are to be met. This is the place help should be obtained above the university/institute level.

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