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Simulation-Based Reliability Analysis For Advanced Designs and Applications. 06/20/2019. Xuguang Shen, Joddy Wang. Outline. Why simulation-based reliability analysis is important SNPS holistic reliability modeling and simulation(MOSRA) Failure rate simulation requirements and flow
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Simulation-Based Reliability Analysis For Advanced Designs and Applications 06/20/2019 Xuguang Shen, Joddy Wang
Outline • Why simulation-based reliability analysis is important • SNPS holistic reliability modeling and simulation(MOSRA) • Failure rate simulation requirements and flow • Showcases
Reliability Requirements Become Critical in Advanced Nodes and Automotive Electronics Increased system complexity and more automotive electronic components require very low failure rate Data based on [K.V. Aadithya, DAC 2011 & Y. Tsukamoto, Renesas] & [S. Natarajan, IEDM 2014, Intel] Advanced process node leave very small design margin [F. Cacho, et. al., “Insights about aging simulation with FastSPICECustomSim (XA) on memory applications,” STMicroelectronics, SNUG, 2016]
ISO26262: Functional Safety for Road Vehicles Automotive Safety Integrity Levels (ASIL) Failure rates determine key fault metrics for ASIL estimation ISO26262 defines ASIL based on • Probability of exposure to harm • Harm severity • Controllability of harmful situation [R. Iacob, et. al., “A simulation-based failure rate analysis for automotive application using CustomSim,” Kilopass Technology/Synopsys Inc., SNUG, 2018.]
Stringent Safety Requirements Need Simulation-based Reliability Analysis Functional Safety ISO26262 AUTOMOTIVE PRODUCT Reliability AEC-Q10X Quality ISO9001 IATF16949 • Simulation-based reliability analysis is a way of modeling and predicting the failure modes and mean time to failure of complex systems • A combined SPICE / FastSPICE reliability solution is a MUST to secure chips w/o overdesign, because SPICE simulation is not suitable for large and complex designs, and FastSPICE solution is required
Holistic Reliability Modeling and Simulation -MOSRA Holistic Reliability-Aging Simulation Flow • Key reliability mechanisms modeling • HCI, BTI, TDDB • Custom reliability modeling • Two-step aging analysis • Age computation and Post-age simulation • Device aging effect and circuit FOM change by age • Inter-play of device self-heating and reliability aging effects • Process variation aware reliability analysis • Gradual aging with custom stress condition aggregation • Capable for block-level and full-chip designs Pre-stress Output “Fresh” simulation w/ Monte Carlo Netlist Fresh model Stress computation SHE computation MOSRA Aging Model Post-stress Output OR Post-stress simulation w/ Monte Carlo API Custom Aging Model Aged Run NMC Fresh Run NMC
Integration of MOSRA in SNPS SPICE/FastSPICE Simulators • Data management is critical for efficient reliability-aging simulation • Multiple-millions components in complex designs, hence FastSPICE performance / capacity • Huge amount of dynamic transient signals need to be processed for aging computation • Millions of unique MOSFETs exists in aged simulation • Custom mission profiles, variability-aware aging analysis lead to many simulations in design/verification cycle • Conventional waveform-based post-processing aging analysis approach does not work • Excessive memory and runtime • Limited to very small circuit only • MOSRA integration is seamless integrated in SPICE/FastSPICE simulators • Shared simulation database and common input/output data model • In memory computation of aging and post-age simulation • Same SPICE/FastSPICE capacity and performance for w/ and w/o aging
Random Failure Simulation • Reliability simulations aim to determine the lifetime of a device or circuit, by adding to the models aging effects such as HCI, NBTI/PBTI, and TDDB. • Induced random variations can mimic the root-cause of real failures during the random failures stage, by setting-up outlier devices that become more sensitive to the aging degradation, within a large population. • Solid line = real lifetime characteristic • Dotted line = variation induced simulated characteristic [R. Iacob, et. al., “A simulation-based failure rate analysis for automotive application using CustomSim,” Kilopass Technology/Synopsys Inc., SNUG, 2018]
Failure Rate Analysis Flow • Worst-case sensitivity analysis • find highest contributors to circuit degradation Circuit Worst-case Sensitivity Analysis (Simulator) Self-heating simulation SHE Simulation (Simulator) • Aging simulation • creating the degraded (aged) models • stress the degraded devices Aging Simulation (Simulator) Large-sample Monte-Carlo • Large-sample Monte-Carlo • random variations on degraded circuit yield parametric or functional failures contributing to the random failure rate Evaluate Failures (Simulator) Estimate Failure Rate • Estimate failure rate • cycle back as required by mission profile
Showcases-1: Reliability-aware Design and Optimization for Analog Blocks • Designers optimize circuit with acceptable degradation with SHE considered. MOSRA w/o Self-heating MOSRA w/ Self-heating MOSRA w/ Self-heating Optimized design Original design Original design SHE SHE SHE_DTEMP = 9.1°C ΔIdsat = 3.7% Δvoffset = 3.3mV SHE_DTEMP = 42°C ΔIdsatHCI+BTI = 16% Δvoffset = 22mV ΔIdsatHCI+BTI = 8.2% [J. Ahn, et. al, “MOSRA aging simulation considering self-heating effect.” Xilinx, Inc., SNUG, 2015]
Showcase-2: Reliability-aware Timing Verification Timing Characterization • SRAM memory – accuracy • Full timing characterization at a given PVT • +4000 timings characterized through fsdb waveform [F. Cacho, et. al., “Insights about aging simulation with FastSPICECustomSim (XA) on memory applications,” STMicroelectronics, SNUG, 2016]
Showcase-3: Reliability-aware IP Verification and Sign-off USB2 Test Case • Without a well defined ageing flow it is difficult to sign-off IPs with confidence, having over-voltage (/Fault) modes cases like USB2 IP [F. Cacho, et. al., “Insights about aging simulation with FastSPICECustomSim (XA) on memory applications,” STMicroelectronics, SNUG, 2016]
Showcase-4: Simulation-based Failure Rate Analysis on An Automotive IP Block ITEST SEooC: current-mode bandgap reference ASIL ASIL ASIL Safety PMHF Goal [FIT] D SPFM C D LFM C D SG1 0.9805 <10 FIT 99.194% >=97% >=99% 99.650% >=80% >=90% [R. Iacob, et. al., “A simulation-based failure rate analysis for automotive application using CustomSim,” Kilopass Technology/Synopsys Inc., SNUG, 2018]
Summary • Neither outdated handbooks nor too generic standards can meet the stringent safety requirements due to system complexity and advanced node development. • Simulation-based reliability analysis is a way of modeling and predicting the failure modes and mean time to failure of complex systems. • Synopsys simulation tool provides comprehensive reliability analysis, with high performance and capacity, makes a simulation-based approach for advanced design and application become possible.
References and Acknowledgement • References • A. Fan, et. al., “Advanced Circuit Reliability Verification for Robust Design”, IRPS, 2019 • R. Wang, et. al., “Random telegraph noise (RTN) in advanced logic devices and circuits,” IEDM, 2018. • R. Iacob, et. al., “A simulation-based failure rate analysis for automotive application using CustomSim,” Kilopass Technology/Synopsys Inc., SNUG, 2018. • K. Khu, et. al., “Custom MOSRA model with gate voltage effect for aging simulation,” TDK-Micronas GmbH and AdMOS GmbH, SNUG, 2018. • H.Thanikasalam, “Self-Heat Aware EM Simulationand Analysis with CustomSim™ for FinFET Devices and Smaller Geometries,” Synopsys, SNUG, 2017. • F. Cacho, et. al., “Insights about aging simulation with FastSPICECustomSim (XA) on memory applications,” STMicroelectronics, SNUG, 2016. • J. Ahn, et. al, “MOSRA aging simulation considering self-heating effect.” Xilinx, Inc., SNUG, 2015. • L. Li, “28nm MOSFET Aging Modeling and Simulation using HSPICE”, Altera/Intel Corp., SNUG, 2011. • Thanks to Zhaoping Chen and Dehuang Wu for their valuable discussions