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Node-to-Network Interface in Scalable Multiprocessors

Node-to-Network Interface in Scalable Multiprocessors. CS 258, Spring 99 David E. Culler Computer Science Division U.C. Berkeley. Racap: Common Challenges. Input buffer overflow N-1 queue over-commitment => must slow sources reserve space per source (credit) when available for reuse?

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Node-to-Network Interface in Scalable Multiprocessors

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  1. Node-to-Network Interfacein Scalable Multiprocessors CS 258, Spring 99 David E. Culler Computer Science Division U.C. Berkeley

  2. Racap: Common Challenges • Input buffer overflow • N-1 queue over-commitment => must slow sources • reserve space per source (credit) • when available for reuse? • Ack or Higher level • Refuse input when full • backpressure in reliable network • tree saturation • deadlock free • what happens to traffic not bound for congested dest? • Reserve ack back channel • drop packets • Utilize higher-level semantics of programming model CS258 S99

  3. Racap: Challenges (cont) • Fetch Deadlock • For network to remain deadlock free, nodes must continue accepting messages, even when cannot source msgs • what if incoming transaction is a request? • Each may generate a response, which cannot be sent! • What happens when internal buffering is full? • logically independent request/reply networks • physical networks • virtual channels with separate input/output queues • bound requests and reserve input buffer space • K(P-1) requests + K responses per node • service discipline to avoid fetch deadlock? • NACK on input buffer full • NACK delivery? CS258 S99

  4. CA CA M P M P Network Transaction Processing Scalable Network • Key Design Issue: • How much interpretation of the message? • How much dedicated processing in the Comm. Assist? Message Input Processing – checks – translation – buffering – action Output Processing – checks – translation – formating – scheduling ° ° ° Communication Assist Node Architecture CS258 S99

  5. Spectrum of Designs • None: Physical bit stream • blind, physical DMA nCUBE, iPSC, . . . • User/System • User-level port CM-5, *T • User-level handler J-Machine, Monsoon, . . . • Remote virtual address • Processing, translation Paragon, Meiko CS-2 • Global physical address • Proc + Memory controller RP3, BBN, T3D • Cache-to-cache • Cache controller Dash, KSR, Flash Increasing HW Support, Specialization, Intrusiveness, Performance (???) CS258 S99

  6. Net Transactions: Physical DMA • DMA controlled by regs, generates interrupts • Physical => OS initiates transfers • Send-side • construct system “envelope” around user data in kernel area • Receive • must receive into system buffer, since no interpretation inCA sender auth dest addr CS258 S99

  7. nCUBE Network Interface • independent DMA channel per link direction • leave input buffers always open • segmented messages • routing interprets envelope • dimension-order routing on hypercube • bit-serial with 36 bit cut-through Os 16 ins 260 cy 13 us Or 18 200 cy 15 us - includes interrupt CS258 S99

  8. Addr Len Status Next Addr Len Status Next Addr Len Status Next Addr Len Status Next Addr Len Status Next Addr Len Status Next Conventional LAN NI Host Memory NIC trncv Data NIC Controller addr TX DMA RX len IO Bus mem bus Proc CS258 S99

  9. User Level Ports • initiate transaction at user level • deliver to user without OS intervention • network port in user space • User/system flag in envelope • protection check, translation, routing, media access in src CA • user/sys check in dest CA, interrupt on system CS258 S99

  10. User Level Network ports • Appears to user as logical message queues plus status • What happens if no user pop? CS258 S99

  11. Example: CM-5 • Input and output FIFO for each network • 2 data networks • tag per message • index NI mapping table • context switching? • *T integrated NI on chip • iWARP also Os 50 cy 1.5 us Or 53 cy 1.6 us interrupt 10us CS258 S99

  12. U s e r / s y s t e m D a t a A d d r e s s D e s t ° ° ° M e m M e m P P User Level Handlers • Hardware support to vector to address specified in message • message ports in registers CS258 S99

  13. J-Machine: Msg-Driven Processor • Each node a small msg driven processor • HW support to queue msgs and dispatch to msg handler task CS258 S99

  14. Monsoon Explicit Token-Store CS258 S99

  15. *T: Network Co-Processor CS258 S99

  16. iWARP: Systolic Computation • Nodes integrate communication with computation on systolic basis • Msg data direct to register • Stream into memory Host Interface unit CS258 S99

  17. Dedicated processing without dedicated hardware design CS258 S99

  18. P P Dedicated Message Processor Network • General Purpose processor performs arbitrary output processing (at system level) • General Purpose processor interprets incoming network transactions (at system level) • User Processor <–> Msg Processor share memory • Msg Processor <–> Msg Processor via system network transaction dest ° ° °  Mem Mem NI NI M P M P User System User System CS258 S99

  19. P P Levels of Network Transaction Network • User Processor stores cmd / msg / data into shared output queue • must still check for output queue full (or make elastic) • Communication assists make transaction happen • checking, translation, scheduling, transport, interpretation • Effect observed on destination address space and/or events • Protocol divided between two layers dest ° ° °  Mem Mem NI NI M P M P User System CS258 S99

  20. Service Network I/O Nodes I/O Nodes Devices Devices 16 175 MB/s Duplex rte MP handler Mem 2048 B ° ° °  EOP Var data NI 64 i860xp 50 MHz 16 KB $ 4-way 32B Block MESI 400 MB/s sDMA $ $ rDMA P M P Example: Intel Paragon CS258 S99

  21. User Level Abstraction (Lok Liu) IQ IQ • Any user process can post a transaction for any other in protection domain • communication layer moves OQsrc –> IQdest • may involve indirection: VASsrc –> VASdest Proc Proc OQ OQ VAS VAS IQ IQ Proc Proc OQ OQ VAS VAS CS258 S99

  22. Msg Processor Events User Output Queues DMA done System Event Send DMA Compute Processor Kernel Dispatcher Rcv DMA Rcv FIFO ~Full Send FIFO ~Empty CS258 S99

  23. Basic Implementation Costs: Scalar 10.5 µs Net • Cache-to-cache transfer (two 32B lines, quad word ops) • producer: read(miss,S), chk, write(S,WT), write(I,WT),write(S,WT) • consumer: read(miss,S), chk, read(H), read(miss,S), read(H),write(S,WT) • to NI FIFO: read status, chk, write, . . . • from NI FIFO: read status, chk, dispatch, read, read, . . . CP MP MP CP 2 1.5 2 2 2 2 Registers 7 wds Cache User OQ User IQ Net FIFO 4.4 µs 5.4 µs 250ns + H*40ns CS258 S99

  24. Virtual DMA -> Virtual DMA sDMA rDMA • Send MP segments into 8K pages and does VA –> PA • Recv MP reassembles, does dispatch and VA –> PA per page Memory CP CP MP Net MP MP 2 2 2 2 1.5 2 Registers 7 wds Cache hdr 400 MB/s User IQ User OQ 400 MB/s 2048 2048 Net FIFO 175 MB/s CS258 S99

  25. Single Page Transfer Rate Effective Buffer Size: 3232 Actual Buffer Size: 2048 CS258 S99

  26. Msg Processor Assessment • Concurrency Intensive • Need to keep inbound flows moving while outbound flows stalled • Large transfers segmented • Reduces overhead but adds latency VAS User Output Queues User Input Queues DMA done System Event Send DMA Compute Processor Kernel Dispatcher Rcv DMA Rcv FIFO ~Full Send FIFO ~Empty CS258 S99

  27. Case Study: Meiko CS2 Concept • Circuit-switched Network Transaction • source-dest circuit held open for request response • limited cmd set executed directly on NI • Dedicated communication processor for each step in flow CS258 S99

  28. Case Study: Meiko CS2 Organization CS258 S99

  29. Shared Physical Address Space • NI emulates memory controller at source • NI emulates processor at dest • must be deadlock free CS258 S99

  30. Case Study: Cray T3D • Build up info in ‘shell’ • Remote memory operations encoded in address CS258 S99

  31. Case Study: NOW • General purpose processor embedded in NIC CS258 S99

  32. T o t a l c o m m u n i c a t i o n l a t e n c y O L O r s O b s e r v e d n e t w o r k D e s t i n a t i o n p r o c e s s o r l a t e n c y e c r u C o m m u n i c a t i o n a s s i s t o s e r N e t w o r k e n i h C o m m u n i c a t i o n a s s i s t c a M S o u r c e p r o c e s s o r T i m e o f t h e m e s s a g e Message Time Breakdown • Communication pipeline CS258 S99

  33. Message Time Comparison CS258 S99

  34. SAS Time Comparison CS258 S99

  35. Message-Passing Time vs Size CS258 S99

  36. Message-Passing Bandwidth vs Size CS258 S99

  37. Application Performance on LU CS258 S99

  38. Application Performance on BT CS258 S99

  39. Message Profile on BT CS258 S99

  40. Reflective Memory • Writes to local region reflected to remote CS258 S99

  41. Case Study: DEC Memory Channel • See also Shrimp CS258 S99

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