Opportunities and Challenges for the Nanometric Design of Post-CMOS Memories

1. Opportunities and Challenges for the Nanometric Design of Post-CMOS Memories Fabrizio Lombardi ITC Endowed Chair Professor Dept of ECE Northeastern University, Boston

2. Memory: today is already the past • CMOS: currently at 28/22nm, soon to move further down in scaling (ITRS) • New commercial markets: GPU, tablet, massive external storage (mostly portable) • Emerging paradigms: multi-value operation, non-volatile RAM, processing-in-memory • Challenges: New designs abound, but not yet a clear winner

3. Evolution of extended CMOS (ITRS) • CMOS is not going away any time soon • More and More-Than Moore • Beyond CMOS Elements More Than Moore  year Beyond CMOS

4. Logic Technologies ITRS 2011 Non-FET, Non Charge-based‘Beyond CMOS’ Devices _______________ Spin Transfer Torque Logic Moving domain wall devices Pseudo-spintronic Devices Nanomagnetic (M:QCA) Negative Cg MOSFET All Spin Logic Molecular Switch Atomic Switch BiSFET Unconventional FETSCharge-based Extended CMOS Devices _______________ Spin FET& Spin MOSFET Negative Cg MOSFET NEMS switch Excitonic FET, Mott FET Tunnel FET I-MOS SET Extending MOSFETs to the End of the Roadmap ___________ CNTFETs Graphene nanoribbons III-V Channel MOSFETs Ge Channel MOSFETs Nanowire FETs Tunnel FET Non-conventional Geometry Devices

5. Memory Technologies ITRS2011 Resistive Memories • Redox Memory • Nanoionic memory • Electrochemical memory • Fuse/Antifuse memory • Molecular Memory • Spin Transfer Torque MRAM • Nanoelectromechanical • Nanowire PCM • Macromolecular (Polymer) Capacitive Memory • Electronic Effects Memory • Charge trapping • Metal-Insulator Transition • FE barrier effects • FeFET Memory

6. Memory technology (ITRS2011)

7. ITRS+IBM: Memories NVM cost/gigabyte ~ $1 (Intel)

8. CMOS vs. Post CMOS Memories • PVT variations • Stability (SNM) concern • Power dissipation • Charge diffusion and collection in the layout • Basic binary operation (supply voltage requirements) • Inability to meet large storage needs • Likely soft errors • Avoid large capital investment, selectively use new/compatible technologies • Preferably, hybrid circuits • Multi-level (multi-bit) operation • Processing in memory (PIM) • Problematic endurance

9. Multi-Level (Multi-bit) Operation • Move to higher radix bases than binary: ternary, quad or eventually octal Bases: • Ternary: used for CAM processing mostly in routers, but also in GPUs (cache) • Quaternary/Octal: increase capacity for massive storage (to replace flash memories) Not efficiently done in CMOS (additional voltage rails and high area/power penalty) Use radically new technologies

10. Emerging Technology Trends • ITRS: memory has alwaysmet stated objectives in the past • Late 2014as crucial initial milestone wrt to performance (power dissipation and density) and design fundamentals. Discuss new (emerging) directions: • Unorthodox technologies (briefly) • Material-based technologies • Focus on non volatile memories

11. Unorthodox Technologies • Innovative operational paradigms for memory using new physics storage phenomena: • QCA (memory in motion); challenge is room temperature operation and CMOS compatibility for manufacturing • SET (controlled transfer of electrons for memory operation purposes) Long term opportunities abound, but grand challenges too Currently applicable mostly to an academic investigation

12. Material-based technologies • Exploit new materials and fabrication methods (CMOS compatible) to meet challenges Additional criteria: • Hybrid operation is usually sought • Robustness to PVT variations/endurance. • New design realms: Multi level (resistance) for increased capacity Ambipolar operation for control APPLICATION: non volatile storage

13. 2011 Memory Application(ITRS) Emerging Research Memory Technology Stand-Alone Embedded Ferroelectric-gate FET X Nanoelectromechanical RAM X X Spin Transfer Torque MRAMX Nanoionic or Redox Memory X X Nanowire Phase Change Memory (PCM) X X Electronic Effects (Charge trapping, Mott) X Macromolecular memory X X Molecular memory X X

14. Non-Volatile Memories • Also know as Resistive RAMs: add (programmable) resistive element(s) to active device(s) (usually 1T1R for simplest non-volatile cell design) Issues: • Resistance range (Rmax-Rmin) • Power dissipation and leakage • Programmability and universal memory feature • Error/defect models (soft and drift) • Endurance (related to read/write operation) • Testing

15. Flash vs NV-RRAMs (late2012) FEATURE NOR NAND PCM MRAM FRAM Capacity 256MB 16GB 32MB 2MB 1MB Random Read Yes No Yes YesYes Random Write No No Yes YesYes Endurance 10^5 10^5-10^3 10^6 10^15 10^14 Management High High Mod No No Error Correction No 1-72 bits * No No Retention(ys) 10 1-10 15 20 5-20 Read Access(ns) 60 60 10 35 60 Prog Access(us) 200 200 20 35 60 Erase Access(ms) 1-100 1-100 50 35 60 Power Mid MidMid Low Low Cell size(F^2) 10 4 4 6-20 4-15 Universal Memory No No Yes Yes Yes

16. Roadmap (IBM 2012)

17. Competition

18. Moving on….. • Flash memory seen as a mature technology, unable to capitalize on scaling and not meeting high density storage for mobile application • Low lifetime due to high-voltage based process • Apple and Anobit (2012) • Additional players: Samsung, Micron, IBM

19. Whyresistive-based memories? Enablestruecrossbarstructures at system-level • Doesnotrequiremany transistorsorother accessdevices • Removesiliconrequirements: • Improvedensity • Reducepowerconsumption • Integrate withprocessors • Reducetotalarea • Crossbar Inc (August 2013): 3D stacking, 1TByte on chip prototype (using FeRRAM) Featuresize=LithonodeF CellSize=4F2 Pitch=2Fforcrossbars P

20. TheMemristor: Prediction FourthFundamental,Two-TerminalCircuitElement LeonChua U.C.Berkeley dφ/dt = v dq/dt= i v Ohm1827 VonKleist 1745 RESISTOR dv=Rdi CAPACITOR dq =Cdv q i MEMRISTOR dφ=Mdq INDUCTOR dφ=Ldi 1831 Faraday 1971 Chua φ

21. Memristor • Resistance depends on direction of voltage or current across it (dϕ = M*dq) • Titanium dioxide film sandwiched between two platinum electrodes; doped operation (HP Labs), 5-10nm in length • Resistance Range • Between Ron and Roff • Roff : Highestresistance • Ron : Lowest resistance

22. Memristor vs. xResistive • Excellent linearity in switching • Resistive range is good • I-V characteristics are also very good • Nanometric dimension (10nm in 2011, 5nm in 2013): very high density potential at extremely low power consumption • Manufacturing compatibility with CMOS • Problem: endurance and leakage (on read)

23. Memristor-Based Memory Cell • Ambipolar control of single memristor • No standby power, no direct path from VDD to GND, only dynamic power dissipation • Less number of transistors than RAM (6T)

24. Performance of Binary Cell Memristor changes its value when reading Roff state Refresh operation is required Write time significantly higher than read

25. Endurance: stuck-at-1 (HP data)

26. Phase Change Memory • Use phases of GTS (chalcogenide alloy) • High current-based process for two phases: amorphous (high R) and crystalline (low R). • No erase-write cycle as for NAND flash (at most 100,000 cycles for enterprise product)

27. Resistive Features • Ron, programming (write) region: intersection of Ron curve with voltage axis is Vh (holding voltage) • Roff, read region: this can be changed by I or V pulse; Roff=Ron exp(toff/t) where t=effective recombination time (constant), toff=non programming time • Vx as intersection point of Ron curve and Rsetcurve, Vx=Vh x Rset/(Rset-Ron) • Typical values: Rset=7k, Rreset=200k, Ron=1k, Vh=0.45v, Rset<Roff<Rreset, t=5nsec

28. Applications • Mobile devices (Samsung) • PCM likely to a be a depository (for less frequently accessed data) next to DRAM for processor design (IBM) • Networking/Communication systems: CAM/TCAM designs • Massive storage for data acquisition systems

29. Commercial news • ISSCC11: Samsung (1-Gbit, 58-nm manufacturing process, low-power double-data-rate nonvolatile memory interface) • ISSCC12 : Samsung (8-Gbit, 20-nm device). • IEDM11: Macronix/IBM (39-nm device with 30-microamp reset current and 10^9 cycling endurance, 128-Mbit) • July 2012: Micron/Numonyx(45 nm PCM for mobile devices in 1 Gb and 512 Mb multichip packages); commercially available

30. PCM Features • Low voltage and moderate current as operational characteristics • Multiple bit operation (at least 2): higher resistance range (M ohms) than other RRAMs • Read Time: 12ns; Write time: 85ns (@45nm) • Soft error highly unlikely to occur for GST • Good endurance (IBM: 1million cycles) and density

31. New Cell Design • Use 1T1P core for both CAM/TCAM • Functionality is at support circuitry • Voltage-based sensing for comparison outcome in search • Use of circuit with ambipolar properties for comparison and control

32. Quantitative Comparison IBM (1/2 PCMs per core), current based operation New cell (1 PCM per core), voltage based operation

33. But ……. • Practical problem: drift of resistance and threshold voltage (when not read or programmed) • Related to crystalline fraction (Cx) in GST • Rpcm=(1-Cx)*Ra+Rc*Cx (Ra >> Rc) • Ra=Rreset • Rc=Rset

34. Resistance Drift • Level drift is more pronounced for high resistance states and non linear wrt time • Problematic for MVL storage (i.e. more than one bit per cell) • Order of resistivity for states remains the same (short term), so avoid overlap in long term.

35. IBM Drift Solution (short-term) • Use advanced modulation coding technique for solving short-term drift (analogous to NAND flash, electrons leak through thin walls of cells and create data read errors). • Apply a voltage pulse based on deviation from desired level and measure resistance. If desired level of resistance is not achieved, apply another voltage pulse and measure again – until achieve the exact level • Only suitable for binary cell storage • It may reduce endurance (multiple writes)

36. Error Codes (mid-ware) • Assume cell independence in drift errors (?). • Data to be encoded not in the programmed state but in the relative order of the states in a small group of cells. • Error in encoding scheme only seen when resistivity levels of states cross each other • Software-based error correction methodologies are then applied (slow) • Reduction in capacity: from 2 bits/cell to 1.57 bits/cell

37. On-going PCM Investigation • Octal base for MVL (noise, crosstalk) and/or single vs multiple storage elements • MVL implications on error detection/correction • Dynamic models of RRAM operation in HSPICE (as related to drift evaluation and mitigation) • At system-level, improve endurance by reducing maximum number of writes to a cell • System-level application modeling (for example “normally-off instantly-on” operation: combining SRAM with PCM)

38. Conclusion • Emergence of new paradigms: resistive RAMs, non-volatile operation, multi-bit storage • Nearly all future memories will utilize new phenomena away from 6T configuration TECHNOLOGY TIME SCALE: • Hybrid implementations will be dominant in the next 5-10 years • 4Q-2014/1Q-2015 as crucial time frame for PCM