Meeting the Design Challenges of Nano-CMOS Electronics

1. Meeting the Design Challenges of Nano-CMOS Electronics e-Science Pilot Project 11 PDRAs 7 Science 4 e-Sci 9 PhD £3.7M EPSRC £4.5M FEC £5.7M with IC Asen Asenov (PI), Richard Sinnott (eSDirector), all partners

2. I have been here before NASA Late 90ies Information Power Grid IPG Glasgow was the overseas node

3. Content • The partners • Motivation • The challenge • The eScience and Grid approach • Current status • The next phase

4. University Partners Advanced Processor Technologies Group (APTGUM) Device Modelling Group (DMGUG) Electronic Systems Design Group (ESDGUS) Intelligent Systems Group (ISGUY) National e-Science Centre (NeSCG) Microsystems Technology Group (MSTGUG) Mixed-Mode Design Group in IMNS (MMDGUE) National e-Science Centre (NeSCE) e-Science NorthWest Centre (eSNW)

5. Industrial Partners Global EDS vendor and world TCAD leader 600 licences for grid implementation, model implementation UK fabless design company and world microprocessor leader Core IP, simulation tools, staff time UK fabless design company and world mixed mode leader Additional PhD studentship for mixed mode design Global semiconductor player with strong UK presence Access to technology, device data, processing Global semiconductor player with strong UK presence Access to technology, device data, processing Global semiconductor player with UK presence CASE studentship, interconnects Trade association of the microelectronics industry in the UK Recruiting new industrial partners and dissemination

6. The Challenge Toshiba 04 Device diversification 90nm: HP, LOP, LSTP 45nm: UTB SOI 32nm: Double gate

7. The variability is becoming a major headache G. Declerck, Keynote talk, VLSI Technol. Symp. 2005

8. Deterministic variability

9. The simulation Paradigm now A 22 nm MOSFET In production 2008 A 4.2 nm MOSFET In production 2023 Statistical variability

10. Vout2 [V] Vout1 [V] Statistical variability

11. Performance/Power/Yield (PPY) trade-off 90nm TN 45nm TN

12. Delivering new results Simple concept Integrated Hierarchical Statistical Design Complex data and workflows Data and Compute Intensive Security Sensitive

13. Objectives • Understanding and forecasting the behaviour, characteristics and variability of next generation nano-CMOS devices using Grid-enabled statistical 3D numerical simulations; • Developing compact model and parameter extraction strategies to capture new device characteristics and variability (based on physical device simulation and early research devices), creating efficient databases for circuit design; • Developing hybrid, Grid based device/circuit simulation techniques applicable to novel nano-CMOS devices with significant variability; • Investigating the impact of new device architectures and device variability on well established design components, sub-systems and systems presently designed using conventional MOSFET architectures; • Developing novel design concepts that cope with increased variability, using specific properties of the new devices; • Learning how electronics researchers can use e-Science technologies to support their work, improve their productivity and enable them to undertake research hitherto impossible.

14. The Development Challenge Electronic design teams currently use different tools, have different data formats, need access to large scale compute resources, generate vast amounts of data, work independently of device engineers. We are building an integrated Grid infrastructure which will revolutionise nanoCMOS design by hiding the complexity of the statistical design making it a completely integrated collaborative process.

15. Dealing with the complexity Year 2-4 ALL Year 1 DMGUG NeSCG NeSCE eSNW

16. Doping Profiles Current Workflow Manual Extraction Of Doping Profiles Synopsis .tif file input

17. Manually generated Input file Atomistic Simulation Current Workflow Simulation Time Of between 1K-50K CPU Hours + + Doping Profiles

18. Synopsys Aurora Atomistic Simulation Current Workflow Simulation Time Of between 1K-50K CPU Hours 200-1000x High Drain Bias IV’s Shell Scripts 100-1000Mb Data 200-1000x Low Drain Bias IV’s

19. Uniform Device Simulation Data Synopsys Aurora Aurora Extraction Strategy Current Workflow 200-1000 Spice Compact Models 200-1000 x Data files Synopsys Aurora Aurora Extraction Strategy

20. Workflow Mgt Framework Data Mgt Framework Workflow Definition Domain Knowledge Capture/Pres. Robust Enactment Data Access/Linkage/Integration Dependency Mgt Data Transformation Job submission/mgt Replication/Movement Computational Steering Metadata/Provenance Visualisation Services Storage/Curation Services Resource Mgt Framework Advanced Security Framework Accounting Components Trust Federation Information Services Identity Management Resource Broking Service Security attributes definition Meta-scheduling Services Policy Decision/Enforcement Points Reservation/Allocation Services Attribute Request/Release Policies Grid stretch focused on realising scientific needs Optimised nanoCMOS Grid Infrastructure

21. Grid service development Meta-data capture/data annotation myGrid workflow => Typical existing application Balsa high-level asynch. circuit synthesis tool used, e.g. for timing verification Expressivity of myGrid Taverna workflow design, FreeFluo enactment? Control loops for optimisation, concurrency needed Feed requirements into OMII-UK for language and enactment engine enhancements

22. Why Shibboleth…? • Can solve licensing issues on Grid • 451 group identified this as key area Grid community must address (…IECnet) • Fine grained authorisation readily supported by Shibboleth and associated technologies such as PERMIS • Is being deployed across UK academia to replace existing Athens system • essential to address gap between research and Grid communities • consider number of active UK e-Science certs vs Athens accounts • Future Grids must be harmonised with wider e-Infrastructure developments • Using the Grid should be no different than using any other internet based system from researcher perspective

23. Glasgow SoA using Edinburgh DIS DyVOSE Delegation Issuing Service Glasgow Edinburgh Condor pool Create new ACs for Glasgow nanoCMOS users/roles LDAP LDAP Glasgow Education VO policies Edinburgh Education VO policies Glasgow nanoCMOS policies Edinburgh nanoCMOS policies PERMIS based Authorisation checks/decisions Job scheduling/ data management Grid BLAST Service Grid BLAST Data Service Edinburgh nanoCMOS services Glasgow nanoCMOS services Edinburgh nanoCMOS data sets Nucleotide + Protein Sequence DB Implemented by Students data input Protein/nucleotide sequence data returned based on student team and Edinburgh policy Glasgow nanoCMOS researchers Grid-data Client

24. Shibboleth-based access to/usage of Grid Resources Roles, attributes, licenses,… needed to make authorisation decision Distinguished Name

25. Shibboleth Enabled Portal - The New Workflow Institutional Login

26. The New Workflow - Unified Simulation Logged In To Portal Shibboleth Attributes determine permissions from attributes

27. The New Workflow - Unified Simulation Stage 1: Create a New Job Ticket This will be automated in the very near future

28. The New Workflow - Unified Simulation Stage 2: File Upload The desired .tif doping profile and atomistic input file are uploaded to the server

29. The New Workflow - Unified Simulation Stage 3: Atomistic Simulation Extraction, mesh generation, simulation, and aurora output phases are now combined

30. The New Workflow - Unified Simulation Stage 4: Aurora Simulation Input the extraction strategy that you wish to use and run aurora.

31. The New Workflow - Unified Simulation Stage 5: Your compact models sir Select the data you require and download it.

32. Other new projects supporting nanoCMOS • OMII-Security Portlets to developing family of JSR-168 compliant portlets for: • scoping of attributes, e.g. only accept Shibboleth attributes and assertions from nanoCMOS partners • dynamic portal configuration management, e.g. configure portal content based on user privileges (security attributes) • attribute release policies, e.g. only release my nanoCMOS specific attributes to nanoCMOS partners • OMII-RAVE • With Cardiff University to integrate Resource Aware Visualisation Environment into OMII • Visualisation key component and will help computational steering

33. MSTGUG Cell fragments Reduce deterministic variability: • develop regular cell fragments • optimise the fragments to reduce deterministic variability Characterise the statistical variability • full 3D simulation of statistical variability in the fragments • timing variability

34. APTGUM Balsa synthesis World’s leading public domain async synthesis tool • developed at UoM • multiple back-end libraries with differing timing assumptions Results from eScience: • improved understandingof economy/reliability • trade-offs on futuretechnologies

35. ISGUY Redundancy for fault tolerant design Different hardware Configurations can meet the fitness criteria

36. ESDGUS Behavioural Analogue Fault Simulation World-leading research • Behavioural Simulation (VHDL-AMS) • Fault Simulation/Modelling Results from eScience: • Grid-enabled simulationtechnology