ATLAS Upgrade Week – Nov. 2010 - CERN

1. Off detector electronics status Vicente González Department of Electronic Engineering University of Valencia ATLAS Upgrade Week – Nov. 2010 - CERN

2. Outline • Architecture baseline • R&D activities • Optical link card • GBT implementation • Xilinx • Altera • FPGA-DSP PU ATLAS Upgrade Week, 8 - 11 November 2010

3. Architecture baseline LINKS WITH Front-End • One FE motherboard (12Ch) would be read-out by 12 GBT links. • 16 SNAP12 connectors for Slice. LINKS to ROS • Through backplane and a Transition Module with the standard defined by ROS. ROD PROCESSOR • Pipeline- Event buffer • Transmission to Pre-Processor • DQ check • Reconstruction PREPROCESSING • Pre-Processor in a different device (FPGA) with links to L1Calo. • InputStage – PreProc high speed links through the motherboard. ATLAS Upgrade Week, 8 - 11 November 2010

4. Architecture baseline • The ROD Processing block may contain additional functionalities. In any case they should be placed either within the ROD PreProcessor or ROD-Processor. • High speed links for data reception • Gain selection • Pipeline L1A receptionEvent Buffer • CELL Energy computation ATLAS Upgrade Week, 8 - 11 November 2010

5. R&D activities • July 2008 TileCal week • We defined 3 phases for our R&D for Upgrade (re-scheduled start 2010 due to funding) • Phase I: Technology analysis • Optical connectors and links, serdes (GBT, FPGA) • Data processing using FPGA with DSP units (Xilinx and Altera) • ATCA interface • Phase II: Design, implementation and test of custom PCBs of reduced ROD system functionalities with chosen technologies • Phase III: ROD prototypes ATLAS Upgrade Week, 8 - 11 November 2010

6. Optical Link Card • Altera Stratix II GX based Mezzanine Card • 1 input SNAP12 connector • 1 output SNAP12 connector • 1 SFP I/O connector (2 Gbps) • Stratix II GX FPGA • Fully compatible connector • ROD PU • OMB ATLAS Upgrade Week, 8 - 11 November 2010

7. Optical Link Card • Present status • Full electrical test completed: OK! • Optical test undergoing (standalone) • Firmware to test Stratix II GX transceivers • Internal loopback: • Use Built-In Self-Test with loopback configuration • BER Test • Physical loopback: • Implement PRBS7 & PRBS23 generator in OLC • Increase data rate 625, 1250, 2500, 3125 to 6250Mbps • BER Test • Loop and speed tests • GBT (already tested with development boards) ATLAS Upgrade Week, 8 - 11 November 2010

8. Optical Link Card SMA • Bit Error Rate & Signal Integrity Test (Next week, Anritsu) • OLC-T (OLC Tester) • 4 layer (2 signal + 2 power plane) • 2 SNAP12 • 24 SMA connectors • 3.3V power supply • Next: integration in OMB and/or ROD • Still working: G-Link implementation in Stratix II GX • Problems with operation frequency in Stratix II • Tests: • Data injection from ROD/OMB • Data processing in FPGA • Future: Data from FE boards ? 3,3V MP1800 12x6.25Gbps OLC SNAP12 ATLAS Upgrade Week, 8 - 11 November 2010

9. GBT implementation - Xilinx • GBT protocol studies in Xilinx Virtex 5/6 FPGAs • Instantiation on Virtex 5 (XC5VFX70T-1FFG1136) • Limit on 10 links • Most limiting parts • RS Decoder on FPGA Slices and LUT • DeMux on BRAM (optimized) • Ongoing work • BER tests • Instantiation studies on Virtex 6 • Work starting in LIP (Lisbon) ATLAS Upgrade Week, 8 - 11 November 2010

10. GBT implementation - Altera • GBT protocol implementation studies in Stratix II and IV • Instantiation on Stratix II GX (EP2SGX90FF1508C3) • 12 transceivers with no problems • Ongoing work • GBT optimization studies ATLAS Upgrade Week, 8 - 11 November 2010

11. GBT implementation - Altera • Stratix IV resource utilization – first results • We don’t expect problems in terms of resources • Next step: • Test compatibility Stratix IV- Stratix II O/F GBT communication ATLAS Upgrade Week, 8 - 11 November 2010

12. FPGA-DSP PU • Evaluate the translation of DSP code from ROD PU to FPGA code • Current ROD uses mezzanine boards DSP based. • Design PU pin-to-pin compatible but FPGA based for ROD or OMB. • Goals • Gain experience and evaluate the limitations of FPGA. • Study the introduction of more advanced algorithm for Phase I Upgrade in TileCal RODs • Applicable to phase II upgrade. ATLAS Upgrade Week, 8 - 11 November 2010

13. Conclusions • We have a first functional board to test optical I/O with SNAP12 connectors • Integrable in ROD and OMB • We have identified the limitations of GBT code • Max. Number of links in Xilinx and Altera • Expect to complete OLC card tests by end of year • Production of two more boards • Proceed with GBT tests in OLC begining 2011 • Integration with OMB and ROD • FPGA PU implementation to test algorithm translation • Upgrade Phase I anf Phase II ATLAS Upgrade Week, 8 - 11 November 2010

14. Thank you for your attention ATLAS Upgrade Week, 8 - 11 November 2010

15. Backup Slides ATLAS Upgrade Week, 8 - 11 November 2010

16. ROD Functional blocks • Input Stage: • Data rate for a 12-PMT motherboard: 12pmt×2redundant×2gains ×12bits ×40MHz = 23.040 Gbs. ( ~12 GBT) – SANP12 • TileCal Slice: 154ch ~13 motherboards ~13 SNAP12 • The link structure will depend on the architecture and the protocol selected for the data transmission. • Pipeline and Derandomizer. • The pipeline length defined by the latency selected. • Implementation of pipelines in FPGA memories seems not to be a constraint for the different possibilities being discussed. • Trigger Preprocessor. • Pulse identification and feature extraction for the L1Calo system. • Link to L1Calo. • ROD Processor. • The ROD processor represents the present Read-Out Drives functionality. • Configuration and Control. • Standard for communication with the boards for configuration, monitoring, communication between boards. • The ATCA standard seems to be the natural replacement for present VME system although the final choice of the standard should be made on an ATLAS level. ATLAS Upgrade Week, 8 - 11 November 2010

17. ROD Processor functionalities • Data synchronization  L1A, BCID, Ttype reception. • Dead-time / Busy logic. • Data reconstruction at L1 rate. • Energy, Phase, QF. • Optimal Filtering in DSP-like FPGA slices. • More sophisticated algorithms should be studied. • Energy Calibration to different Units. • Histogramming and Monitoring. • Data Quality check. • Level 2 trigger algorithms • MuTag, Total ET • Raw data (compression?) for offline reconstruction. • Communication with ROS. ATLAS Upgrade Week, 8 - 11 November 2010

18. GBT resources in Virtex 5 ATLAS Upgrade Week, 8 - 11 November 2010

19. GBT implementation - Altera • Stratix IV resource utilization – preliminary ATLAS Upgrade Week, 8 - 11 November 2010