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III-V FET Channel Designs for High Current Densities and Thin Inversion Layers

This paper discusses the design of III-V FET channels with thin inversion layers and high current densities for improved device performance. Various approaches, including the use of different valley orientations and stacked wells, are explored to increase the density of states and achieve higher drive currents. The challenges and solutions for scaling III-V FETs are also addressed.

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III-V FET Channel Designs for High Current Densities and Thin Inversion Layers

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  1. 2010 IEEE Device Research Conference, June 21-23, Notre Dame, Indiana III-V FET Channel Designs for High Current Densities and Thin Inversion Layers Mark Rodwell University of California, Santa Barbara Coauthors: W. Frensley: University of Texas, Dallas S. Steiger, S. Lee, Y. Tan, G. Hegde, G. KlimekNetwork for Computational Nanotechnology, Purdue University E. Chagarov, L. Wang, P. Asbeck, A. Kummel, University of California, San Diego T. BoykinUniversity of Alabama, HuntsvilleJ. N. SchulmanThe Aerospace Corporation, El Segundo, CA. Acknowledgements: Herb Kroemer (UCSB), Bobby Brar (Teledyne) Art Gossard (UCSB), John Albrecht (DARPA) rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax

  2. Thin, high current density III-V FET channels InGaAs, InAs FETs THz & VLSI need high current low m*→ high velocities FET scaling for speed requires increased charge density low m* →low charge density Density of states bottleneck (Solomon & Laux IEDM 2001) → For < 0.6 nm EOT, silicon beats III-Vs Open the bottle ! low transport mass → high vcarriermultiple valleys or anistropic valleys → high DOSUse the L valleys.

  3. Goal: double transistor bandwidth when used in any circuit → reduce 2:1 all capacitances and all transport delays→ keep constant all resistances, voltages, currents Simple FET Scaling gate-source, gate-drain fringing capacitances: 0.15-0.25 fF/mm must increase gate capacitance/area must reduce gate length

  4. FET Scaling Laws Changes required to double device / circuit bandwidth. laws in constant-voltage limit: Current densities should doubleCharge densities must double

  5. Semiconductor Capacitances Must Also Scale

  6. Calculating Current: Ballistic Limit Do we get highest current with high or low mass ?

  7. Drive current versus mass, # valleys, and EOT InGaAs MOSFETs: superior Id to Si at large EOT.InGaAs MOSFETs: inferior Id to Si at small EOT. Solomon / Laux Density-of-States-Bottleneck → III-V loses to Si.

  8. Transit delay versus mass, # valleys, and EOT Low m* gives lowest transit time, lowest Cgs at any EOT.

  9. Low effective mass also impairs vertical scaling Shallow electron distribution needed for high Id, high gm / Gds ratio, low drain-induced barrier lowering. Energy of Lth well state For thin wells, only 1st state can be populated. For very thin wells, 1st state approaches L-valley. Only one vertical state in well. Minimum ~ 3 nm well thickness. → Hard to scale below 10-16 nm Lg.

  10. III-V Band Properties, normal {100} Wafer

  11. Consider instead: valleys in {111} Wafer

  12. Valley in {111} wafer: with quantization in thin wells

  13. {111} G-L FET: Candidate Channel Materials

  14. Standard III-V FET: G valley in [100] orientation 3 nm GaAs wellAlSb barriers G=0 eVL=177 meVX[100]= 264 meVX[010] = 337 meV

  15. 1st Approach: Use both G and L valleys in [111] 2.3 nm GaAs wellAlSb barriers[111] orientation G= 41 meVL[111] (1)= 0 meVL[111] (2)= 84 meVL[111] , etc. =175 meVX=288 meV

  16. Combined G-L wells in {111} orientation vs. Si combined (G -L) transport 2 nm GaAs G /L well→ g =2, m*/m0=0.07 4 nm GaSb G /L well→ mG*/m0=0.039, mL,t*/m0=0.1

  17. 2nd Approach: Use L valleys in Stacked Wells Three 0.66 nm GaAs wells0.66 nm AlSb barriers [111] orientation L[111](1) = 0 meVL[111](2)= 61 meVL[111](3)= 99 meV G=338 meVL[111], etc =232 meVX=284 meV

  18. Increase in Cdos with 2 and 3 wells

  19. 3 High Current Density (111) GaAs/AlSb Designs

  20. Concerns Nonparabolic bands reduce bound state energies Failure of effective mass approximation:1-2 nm wells 1-2 monolayer fluctuations in growth → scattering→ collapse in mobility

  21. Purdue Confirmation

  22. Steiger, Klimeck, BoykinRyu, Lee, Hegde, Tan Purdue Confirmation

  23. 1-D FET array = 2-D FET with high transverse mass 2-D FET 1-D Array FET Weak coupling → narrow transverse-mode energy distribution→ high density of states

  24. 3rd Approach: High Current Density L-Valley MQW FINFETs

  25. 4th Approach: {110} Orientation→ Anisotropic Bands transport

  26. Anisotropic bands, e.g. {110} Transport in {110} oriented L valleys

  27. THz FET scaling: with & without increased DOS

  28. Scaled FET performance: fixed vs. increasing DOS fmax ft SCFL divider speed mA/mm→ VLSI metric Increased density of states needed for high drive current, fast logic @ 16, 11, 8 nm nodes

  29. 10 nm / 3 THz III-V FETs: Challenges & Solutions gate dielectric:decrease EOT 2:1 To double the bandwidth: channel: keep same velocity, butthin channel 2:1increase density of states 2:1 S/D access regions:decrease resistivity 2:1 S/D regrowth Wistey et alSingisetti et al

  30. (end)

  31. Purdue Confirmation

  32. MOSFET Scaling Laws

  33. 2.0 nm GaAs well, AlAs barriers, on {111} GaAs

  34. GaSb well, AlSb barriers, on {110} GaSb

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