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HKN ECE 342 Review Session 1. Anthony Li Keshav Harisrikanth. KVL/KCL. Sum of all voltages in a loop is 0 Sum of current entering a node equals sum of current exiting a node. Incremental/Small Signal Model.
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HKN ECE 342 Review Session 1 Anthony Li Keshav Harisrikanth
KVL/KCL • Sum of all voltages in a loop is 0 • Sum of current entering a node equals sum of current exiting a node
Incremental/Small Signal Model • Can be numerically derived from Taylor Series approximation (up to first-order term) • Taylor Series:
MOSFET’s • NMOS • PMOS
MOSFET Operating Point • Three regions of operation: • Cutoff (VGS < VT): ID = 0 • Linear/Triode (VGS > VT, VDS < VGS - VT): • Saturation (VGS > VT, VDS > VGS - VT): • Note:
MOSFET Incremental Model Transconductance:
Current Mirrors • Transistors sharing the same “mirror” current – just a ratio of transistor sizing.