1 / 11

Lessons from Adaptive Level One Accelerator (ALOA) System Implementation

Lessons from Adaptive Level One Accelerator (ALOA) System Implementation. Umesh D. Patel, Clifford Brambora, Parminder Ghuman NASA/Goddard Space Flight Center, Code 564, Greenbelt, MD 20771. Topics. ALOA system overview Review of Design Process Lessons learned Conclusions.

xuan
Download Presentation

Lessons from Adaptive Level One Accelerator (ALOA) System Implementation

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Lessons from Adaptive Level One Accelerator (ALOA) System Implementation Umesh D. Patel, Clifford Brambora, Parminder GhumanNASA/Goddard Space Flight Center, Code 564, Greenbelt, MD 20771

  2. Topics • ALOA system overview • Review of Design Process • Lessons learned • Conclusions C. Brambora Paper D1

  3. Commercial Antenna and Workstations Level 0 Processing System • Digital Receiver Card • Return Link Processor Card • Forward Link Simulator Card Level 1 Processing System ALOA Wildforce Board Science Data Product Generation ALOA System overview MODIS Adaptive Level One Accelerator (ALOA) C. Brambora Paper D1

  4. ALOA System Overview C. Brambora Paper D1

  5. Review of Design Process • Profiling the C code • Identify the computation intensive sections • FPGA Computer selection • Select the architecture best fit for algorithm • Precision analysis • Mapped all floating-point operators to fixed-point operators • Used “rule of the thumb” of 1/10 of percent accuracy C. Brambora Paper D1

  6. Review of Design Process • Algorithm partitioning and mapping • Algorithm was partitioned between the host and FPGA computer • Data flow diagram was prepared • Incremental design and testing • Whole design is broken into smaller and simpler tasks C. Brambora Paper D1

  7. Algorithm Mapping for reflective Calibration C. Brambora Paper D1

  8. Data Flow Diagram C. Brambora Paper D1

  9. Lessons learned • The higher the FPGA computer I/O bandwidth, the higher the potential for computation acceleration • Extraction of algorithm from C code is an inefficient method • Migrating the C language based implementation to a JAVA based implementation didn’t prove to be advantageous C. Brambora Paper D1

  10. Lessons learned (2) • Basic mathematical operators generated by the Xilinx Core Generator tool proved to be extremely helpful • No single tool provide automated design process • No single FPGA Computer architecture will best fit all algorithms C. Brambora Paper D1

  11. Conclusions How would we implement ALOA System today ??? • Obtain the algorithm in mathematical form • Use System Generator tool for fixed-point analysis and FPGA design • Use incremental approach for design and testing • Explore some alternative architectures – DIMM mounted FPGA computer (Nuron) C. Brambora Paper D1

More Related