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Analog Circuit Design Techniques at 0.5 V

Analog Circuit Design Techniques at 0.5 V. Shouribrata Chatterjee. Department of Electrical Engineering, Indian Institute of Technology Delhi. 1.2 mm. 1 mm. Biasing circuits. Filter. PLL. 1.2 mm. 1 mm. Master. Slave. OTAs. Track-and-holds. Biasing circuits.

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Analog Circuit Design Techniques at 0.5 V

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  1. Analog Circuit Design Techniques at 0.5 V Shouribrata Chatterjee Department of Electrical Engineering, Indian Institute of Technology Delhi

  2. 1.2 mm 1 mm Biasing circuits Filter PLL 1.2 mm 1 mm Master Slave OTAs Track-and-holds Biasing circuits Fully integrated 0.5 V analog circuits • Gate and body-input OTAs • PLL-tuned filter and track-and-hold circuits • Operation from 0.45 V to 0.6 V • True low-voltage circuits for the nano-scale era

  3. Thin Oxide Vdd Thick Oxide Vdd Volts Threshold Technology node [nm] [ITRS'04] Deep-sub-1 V for nano-scale CMOS devices

  4. Latch-up • Positive feedback structure if Q2 switches ON • Requires VDD to be more than at least one diode drop

  5. Body effect

  6. Body effect

  7. 0.5 V OTA design

  8. 0.5 V 0.15 V -0.15 V 0.3 - 0.35 V 0.8 V 0.15 V 0.65 V 0.15 V OTA design challenges Assuming|VGS - VT |≈ 0.15 V,|VT | = 0.5 V

  9. 0.25 V 0.25 V 0.5 V 0.25 V 0.1 V 0.15 - 0.35 V Basic body-input OTA stage [S. Chatterjee, Y. Tsividis, P. Kinget, ESSCIRC 2004]

  10. Pole splitting using Miller capacitor Two-stage fully-differential body-input OTA

  11. Layout Micro-photograph Chip prototype • 0.18 µm CMOS mixed-signal process: • Standard nMOS and pMOS devices, • High resistivity poly resistors, • MIM capacitors. • Die Area: 0.026 sq. mm

  12. 0.1 V 0.5 V 0.1 V 0.25 V 0.15 - 0.35 V 0.4 V 0.4 V 0.4 V Basic gate-input OTA Assuming|VGS - VT |≈ 0.15 V, |VT | = 0.5 V

  13. 0.5 V gate-input OTA gain stage [S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC 2005]

  14. 0.4 V 0.4 V 0.25 V 0.4 V Two stage gate-input OTA • Common-mode output of first stage is 0.4 V • 55 dB gain, 15 MHz GBW, 60º PM for diff 10pF load

  15. Two-stage gate-input fully differential 0.5 V OTA with Miller compensation

  16. 0.5 V Rb = 2/3 • Ri||Rf 0.4 V 0.25 V 0.25 V 0.4 V 0.5 V Setting common-mode voltages for the gate-input OTA

  17. Gate-input OTA automatic biasing circuits

  18. Vin Vout Vout[V] Vin [V] Error amplifier for biasing • 20 kHz GBW for 1 pF load • 2 µA current • Controlled body voltage sets the amplifier threshold [S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC 2005]

  19. Level shift biasing circuit (Simplified OTA) Vbn generating circuit On-chip biasing circuits

  20. VNR generating circuit Replica of OTA stage 1 Increasing VNR Output diff voltage [V] Input differential voltage [mV] OTA dc transfer characteristics and VNR generation

  21. 0.5 V body and gate-input OTA measurements

  22. DC gain: 52 dB GBW: 2.5 MHz Measurement Simulation Phase Margin: 450 Frequency [Hz] Body-input OTA open-loop frequency response

  23. 350 mV (Automatic gain-boosting) Increasing gain-boosting bias 50 mV Gain [dB] GBW: 10 MHz Frequency [Hz] Gate-input OTA open-loop frequency response

  24. 0.5 V measured performance summary Open loop Closed loop

  25. 0.5 V weak-inversion varactor for frequency tuning

  26. Body (Vtune) VGS = 0.25 V Cgs/Cox Gate (0.4 V) Source Drain (0.25 V) VGS = 0.20 V VGS = 0.15 V Vgate-Vtune or VGB[V] Filter tuning challenges at 0.5 V • Gm-C • MOSFET-C • Switching banks of R’s and C’s • Varactor-R techniques [S. Chatterjee, Y. Tsividis, P. Kinget, VLSI 2005]

  27. Charge Sheet Model Channel doping = 3.5e17/cm3 VFB = -1 V Increasing VGBfrom -0.1V to 0.4V Cgs/Cox Region of interest for use as weak-inversion varactor VGS [V] Capacitance characteristics

  28. 135 kHz Gain [dB] 280 kHz Frequency [Hz] 5th order elliptic low-pass filter using tunable integrators [S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC 2005]

  29. Block diagram

  30. 1 mm Filter PLL 1 mm OTAs Biasing circuits Chip micrograph • 0.18 µm CMOS • MIM capacitors • High-res resistors • Standard VT • Triple well devices

  31. Gain [dB] Frequency [Hz] Measured filter response for different supply voltages

  32. Gain [dB] Notch at 120kHz, -42dB 200kHz, -50dB Frequency [Hz] Filter tuning through the varactor

  33. Filter performance summary at 27C • Measured CMRR (10 kHz common mode tone): 65 dB • Measured PSRR (10 kHz tone on power supply): 43 dB Functionality tested from 5C to 85C at 0.5 V

  34. 0.5 V fully-differential track-and-hold circuit

  35. Large VDD Small VDD Enough headroom No headroom Sampling challenges at 0.5 V

  36. vin vout [Ishikawa, JSSC Dec 89] Basic track-and-hold architecture • Voltages on both sides of the switches are signal independent. • Signal-independent charge injection. • Does this work at a 0.5V power supply?

  37. Differential implementation at 0.5V • Gate-input OTA used. • Track phase during 1, hold phase during 2. • During track phase, pole and zero cancel out to enable fast response. • pMOS switches have VTof about 0.5V.

  38. Track mode operation • Resistors to 0.5V maintain required OTA input CM voltage of 0.4V. • To enable better switching, both gate and body of the switch are used. • No voltage swing on either side of the switches.

  39. Hold mode operation • Gate and body of the switch used for better switching. • No signal swing on both sides of the switches. • OTA input voltages held constant.

  40. 0.5 V fully-differential OTA [S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC’05, JSSC Dec’05]

  41. 0.5 V fully-differential OTA [S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC’05, JSSC Dec’05]

  42. 0.5 V fully-differential OTA [S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC’05, JSSC Dec’05]

  43. 0.5 V fully-differential OTA [S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC’05, JSSC Dec’05]

  44. Design targets • 1MHz of sampling rate. • 60 dB of signal to noise-distortion range. • OTA worst case gain-bandwidth of 20MHz. • Worst case slew rate of 6V/µs. • Sampling capacitor of 1pF. • To be designed using devices with VT 0.5 - 0.6V • Switches sized to optimize resistance for settling, minimize noise, feedthrough.

  45. CLKA [Vorenkamp, JSSC Jul 92] CLKB Test plan: two track-and-holds in cascade

  46. Prototype-chip block diagram

  47. 1.2mm Biasing circuits 1.2mm Master Slave Track-and-holds Track-and-hold chip micrograph • 0.25µm CMOS • |Vt|= 0.6V • MIM capacitors • Triple-well devices • High-resistivity resistors • Chip fabrication supported by Philips.

  48. Output at FS/2 x 1/128 Input at FS/2 x 127/128 Output transient [V] Time [sec] 62dB simulated dynamic range SNDR [dB] Input amplitude [dBV] Some simulated results at 0.5V, 1M-sample/sec

  49. Output differential voltage [mV] Time [µsec] Re-sampled 25kHz output for a 200mVpp input at 475kHz Typical time-domain output waveform

  50. SNDR [dB] Input differential rms [dBV] Measured SNDR

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