CMOS Detector Technology

CMOS Detector Technology Alan Hoffman Raytheon Vision Systems Markus Loose Rockwell Scientific Vyshnavi Suntharalingam MIT Lincoln Laboratory Scientific Detector Workshop, Sicily 2005

Outline Markus Loose • General Concept & Architecture • Common Features of CMOS Sensors • Stitching Technology Enables Large Arrays • Monolithic CMOS • Hybrid CMOS • History of Hybrid CMOS • ROIC Input Cells • Detector Materials & Properties • Low Noise Through Multiple Sampling • CMOS Processing and General Limitations • Emerging Technologies • Vertical Integration • Geiger-Mode Avalanche Photodiode Arrays • Comparison: CMOS vs. CCD for Astronomy Alan Hoffman Vyshi Suntharalingam

InSb 2K x 2K, 25 µm pixels HgCdTe 2K x 2K, 20 µm pixels 3D stacked CMOS wafer sandbox HgCdTe 2K x 2K, 18 µm pixels Monolithic CMOS 4K x 4K, 5 µm pixels HgCdTe 4K x 4K mosaic, 18 µm pixels Collection of High-Performance CMOS Detectors

Photodiode Photodiode Amplifier + Pixel Charge generation, charge integration & charge-to-voltage conversion Charge generation & charge integration Multiplexing of pixel voltages: Successively connect amplifiers to common bus Array Readout Charge transfer from pixel to pixel • Various options possible: • no further circuitry (analog out) • add. amplifiers (analog output) • A/D conversion (digital output) Sensor Output Output amplifier performs charge-to-voltage conversion General CMOS Detector Concept CCD Approach CMOS Approach

General Architecture of CMOS-Based Image Sensors Bias Generation & DACs (optional) Vertical Scanner for Row Selection Control & Timing Logic (opt.) Pixel Array A/D conversion (optional) Digital Output Horizontal Scanner / Column Buffers Analog Amplification Analog Output

Common CMOS Features • CMOS sensors/multiplexers utilize the same process as modern microchips • Many foundries available worldwide • Cost efficient • Latest processes available down to 0.13 µm • CMOS process enables integration of many additional features • Various pixel circuits from 3 transistors up to many 100 transistors per pixel • Random pixel access, windowing, subsampling and binning • Bias generation (DACs) • Analog signal processing (e.g. CDS, programmable gain, noise filter) • A/D conversion • Logic (timing control, digital signal processing, etc.) • Electronic shutter (snapshot, rolling shutter, non-destructive reads) • No mechanical shutter required • Low power consumption • Radiation tolerant (by process and by design)

Windowing Subsampling Random Read Binning* • Reading of one or multiple rectangular subwindows • Used to achieve higher frame rates (e.g. AO, guiding) • Skipping of certain pixels/rows when reading the array • Used to obtain higher frame rates on full-field images • Random access (read or reset) of certain pixels • Selective reset of saturated pixels • Fast reads of selected pixels • Combining several pixels into larger super pixels • Used to achieve lower noise and higher frame rates * Binning is typically less efficient in CMOS than in CCDs. Special Scanning Techniques Supported by CMOS • Different scanning methods are available to reduce the number of pixels being read: • Allows for higher frame rate or lower pixel rate (reduction in noise) • Can reduce power consumption due to reduced data

Full field row Window Full field row Full field row Full field row Full field row Window Window Astronomy Application: Guiding • Special windowing can be used to perform full-field science integration in parallel with fast window reads. • Simultaneous guide operation and science data capture within the same detector. • Two methods possible: • Interleaved reading of full-field and window • No scanning restrictions or crosstalk issues • Overhead reduces full-field frame rate • Parallel reading of full-field and window • Requires additional output channel • Parallel read may cause crosstalk or conflict • No overhead  maintains maximum full-field frame rate

Electronic Shutter: Snapshot vs. Rolling Shutter • Rolling Shutter (Ripple Read) • Each row starts and stops integrating at a different time (progressively). • Typically less transistors per pixel and lower noise. • Snapshot Shutter • All rows are integrating at the same time. • Typically more transistors per pixel and higher noise. Row 1 integration time Row 1 integration time integr Row 2 integration time Row 2 integration time inte Row 3 integration time Row 3 integration time int Row 4 integration time Row 4 integration time i Row 5 integration time Row 5 integration time Read pixels of selected row Read pixels of selected row stop integrating start integrating stop integrating start integrating start 2nd integration if pixel supports “integrate while read”

horiscan1 horiscan2 V 1 array array array V 2 array array array horiscan2 horiscan1 V 3 array array array V 1 V 2 V 3 array Stitching Enables Large Sensor Arrays • The small feature size of modern CMOS processes limits the maximum area that can be exposed in one step (so-called reticle) to about 22 mm. • However, larger chips can produced by breaking up the design into smaller sub-blocks that fit into the reticle. Stitched CMOS Sensor • Sub-blocks are exposed one after another • Some blocks are used multiple times • Ultimate limit is given by wafer size Reticle 22mm

Single Chip Discrete Electronics Dual Chip • Assembly of discrete chips and boards • Large, higher power • Reusable, modular, only PCB design required • All electronics integrated in sensor chip • Small, low system power • Not always desirable (high design effort, glow) • All electronics integrated in a single companion chip • Small, low system power • Can be placed next to detector => low noise Detector Array Detector Array Detector Array Requires ext. ADC, bias and/or clock generation Includes ADC, bias & clock generation Requires ext. ADC, bias and/or clock generation Analog output Bias Clocks Analog output Bias Clocks DAC ADC Digital data Logic ASIC Memory Digital data Digital data Acquisition System Acquisition System Acquisition System CMOS-Based Detector Systems • Three possible CMOS Detector Electronics Configurations

Reset SF PD Select Read Bus Reset SF TG Pinned PD p+ n+ n+ p-sub Select Read Bus Monolithic CMOS • A monolithic CMOS image sensor combines the photodiode and the readout circuitry in one piece of silicon • Photodiode and transistors share the area => less than 100% fill factor • Small pixels and large arrays can be produced at low cost => consumer applications (digital cameras, cell phones, etc.) 3T Pixel photodiode transistors 4T Pixel

2 Mpixel HDTV CMOS Sensor Quantum Efficiency of a CMOS sensor Si PIN NIR AR coating Si PIN UV AR coating • Microlenses increase fill factor: 3T pixel w/ microlenses photodiode Complete Imaging Systems-on-a-Chip • Monolithic CMOS technology has enabled highly integrated, complete imaging systems-on-a-chip: • Single chip cameras for video and digital still photography • Performance has significantly improved over last decade and is better or comparable to CCDs for many applications. • Especially suited for high frame rate sensors (> Gigapixel/s) or other special features (windowing, high dynamic range, etc.) • However, monolithic CMOS is still limited with respect to quantum efficiency: • Photodiode is relatively shallow => low red response • Metal and dielectric layers on top of the diode absorb or reflect light => low overall QE • Backside illumination possible, but requires modification of CMOS process

Indium bump hybrid invented, circa 1975 CMOS ultimately "won" due to ease of design and availability of foundries CMOS Processing Evolution for Hybrid Focal Planes 1975 1980 1985 1990 1995 2000 2005 MOS w/surface channel CCD PMOS or NMOS CMOS

Mature interconnect technique: Over 4,000,000 indium bumps per SCA demonstrated 99.9% interconnect yield Detector Array Detector Array Indium bump 16,000,000 Sensor Chip Assembly (SCA) Structure:Hybrid of Detector Array and ROIC Connected by Indium Bumps Silicon Readout Integrated Circuit (ROIC) • Also called a Focal Plane Array (FPA) or Hybrid Array

CMOS SCA Revolution • Large CMOS hybrids revolutionized infrared astronomy • Growth in size has followed "Moore's Law" for over 20 years • 18 month doubling time

SFD DI reset switch CTIA Output S/F FET input FET Cint detector enable switch load Cfb driver Input Circuit Schematics

Three Most Common Input Circuits for CMOS ROICs Circuit SFD (Source Follower per Detector) also called "Self Integrator" CTIA (Capacitance Transimpedance Amplifier) DI (Direct Injection) Advantages • simple • low noise • low FET glow • low power • very linear • gain determined by ROIC design (Cfb) • detector bias remains constant • large well capacity • gain determined by ROIC design (Cint) • detector bias remains constant • low FET glow • low power Disadvantages • gain fixed by detector and ROIC input capacitance • detector bias changes during integration • some nonlinearity • more complex circuit • FET glow • higher power • poor performance at low flux Comments Most common circuit in IR astronomy Very high gains demonstrated Standard circuit for high flux

Si PIN InGaAs SWIR HgCdTe MWIR HgCdTe InSb LWIR HgCdTe Si:As IBC Temperature and Wavelengths ofHigh Performance Detector Materials Approximate detector temperatures for dark currents << 1 e-/sec

Detector Material Choices for CMOS Hybrid Arrays Spectral Range*, m 0.4 – 1.0 0.9** – 1.7 0.9** – 1.7 0.9** – 2.5 0.9** – 5.2 5 – 10 0.4 – 5.2 5 – 28 Operating Temp***, K ~ 200 ~ 130 ~ 140 ~ 90 ~ 50 ~ 25? ~ 35 ~ 7 General Comments • All detectors can have: • 100% optical fill factor • 100% internal QE (total QE depends on AR coat) • Exception: Si:As is 40-70% between 5 and 10 m • ROICs are interchangeable among detectors (except Si:As) • HgCdTe and InGaAs require special packaging due to CTE mismatch between detector and ROIC Detector Material Si PIN InGaAs HgCdTe: 1.7m 2.5 m 5.2 m 10 m InSb Si:As IBC (BIB) * Long wave cutoff is defined as 50% QE point ** Spectral range can be extended into visible range by removing substrate *** Approximate detector temperatures for dark currents << 1 e-/sec

Noise in CMOS SCA/Hybrids • Temporal • White (uncorrelated) noise • Reduced by multiple sampling • 1/f (drift) noise • Not a limiting factor in most astronomy focal planes • Fixed pattern noise • Caused by residual non-uniformity after calibration • Can be reduced (eliminated?) by calibrating at multiple points in the dynamic range • Random Telegraph Signal (RTS) • Randomly occurring charge trapping/detrapping events • Process, design and characterization dependent • Personal experience: have not seen this

CMOS SCA Sampling Techniques Reset begins integration Voltage ramp for a single pixel • Periodic sampling of detector signal possible during a long integration • Two general methods of white noise reduction by multiple sampling • Fowler sampling: average 1st N samples and last N samples; then subtract • Sample up the ramp (SUTR): fit line (or polynomial) to all samples

Example of Noise vs Number of Fowler Samples 100 sec integrations in all cases Bare multiplexer 2 e- Data courtesy of Dr. Craig McMurtry, University of Rochester

Example of Fowler and SUTRSampling in Uncorrelated (White) Noise Limit 6% difference Peak at Fowler N/3

Hybrid CMOS Summary • CMOS ROIC • Wide choice of processing foundries and analog circuits • "System on a chip" is possible • Clocks & biases • A/D & DAC • Any digital function • Detectors • Wide choice of detector materials • Interchangeability among detectors and ROICs • SCAs • Up to 4K x 4K arrays successfully hybridized

Process Comparison 2mm 2mm 2mm Four-Poly OTCCD 180-nm SRAM cell Stacked via to poly

<0.25mm CMOS Technology Features

Periphery Pixel CMOS Pixel Process Flow ONO spacer Poly STI Double S/D imp Oxide Deposit oxide Spin coat organic material Organic material Etch-back and remove oxide Photo resist Remove organic material Pattern oxide (photo/etch) Silicide Form silicide on peripheral devices Adapted from S. Wuu, TSMC

Cross Sectional TEM Photograph of Pixel Silicide gate 0.3um 0.4um non-silicide S/D Courtesy S. Wuu, TSMC

photodiode OUT RST VDD ROW VDD ROW OUT RST n+ p+ Field Oxide n-Well p-well p-epi p+ Substrate Limitations of Standard Bulk CMOS APS Pixel Layout • Fill factor tradeoff • Photodetector and pixel transistors share same area • PD from Drain-Substrate or Well-Substrate diode • Low photoresponsivity • Shallow, heavily doped junctions • Limited depletion depth • Absorption and reflection in poly, metal, and oxide layers • Surface recombination at Si/SiO2 interface • QE*FF > 60% is good, many < 20% • High leakage • LOCOS/STI, salicide • Transistor short channel effects • Substrate bounce and transient coupling effects

pixel Advantages of Vertical Integration Conventional Monolithic APS 3-D Pixel Light • Pixel electronics and detectors share area • Fill factor loss • Co-optimized fabrication • Control and support electronics placed outside of imaging area PD pixel PD 3T Addressing ROIC Processor Addressing A/D, CDS, … • 100% fill factor detector • Fabrication optimized by layer function • Local image processing • Power and noise management • Scalable to large-area focal planes

10 mm 10 mm 10 mm Approaches to 3D Integration (To Scale) Tier-1 3D-Vias 3D-Vias Tier-2 Photo Courtesy of RTI Bump Bond used to flip-chip interconnect two circuit layers Two-layer stack using Lincoln’s SOI-based vias Two-layer stack with insulated vias through thinned bulk Si

pixel Foundry Chip 8 mm Tile with Daughter Chip Four-Side Abuttable Goal • 3-D CMOS imagers tiled for large-area focal planes • Foundry fabricated daughter chip bump bonded to non-imaging side Tiled Array mechanical mockup

Pixel 5 mm Cross Sections Through 3-D Imager SOI-CMOS (Wafer 2) SEM cross section Photodiode (Wafer 1) 8 mm decorated Transistor CMOS Vias 3D-Via Bond Interface Diode

Four-Side Abuttable Vertically Integrated Imaging Tile • Wafer-Scale 3D circuit stacking technology • Silicon photodetector tier • SOI-CMOS address and readout tier • Per-pixel 3D interconnections • 1024x1024 array of 8mmx8mm pixels • 100% fill factor • >1 million vertical interconnections per imager Front Illuminated Back Illuminated Presented at 2005 ISSCC

Geiger-Mode Imager: Photon-to-Digital Conversion Digitallyencodedphotonflight time Pixel circuit Digital timing circuit • Quantum-limited sensitivity • Noiseless readout • Photon counting or timing photon APD/CMOS array APD Lenslet array Focal-plane concept

Npe= 105 3-D Laser Radar Sensor Development • Objective: single flash, non-scanned 3D area imager • Pixel stores range, not intensity, information • 3-D imaging provides • Robust object recognition • relatively independent of lighting, reflectivity • Separates objects behind foliage, camouflage 3-D Brassboard image Active intensity image SUV SUV behind camouflage

Technology Development Evolution Discrete 4x4 arrays 4x4 arrays wire bonded to 16-channel CMOS readout 32x32 arrays fully integrated with 32x32 CMOS readout APD’s 1996 2001

Tier-3: 1.5V FDSOI CMOS Tier-2: 3.3V FDSOI CMOS APD APD Tier-1: Avalanche Photodiode VISA APD Pixel Circuit (~250 transistors/pixel) Pseudorandom counter circuit APD drive/sense circuit Avalanche PD 3D Laser Radar Focal Plane (3D)2 • Laser radar focal plane based on single-photon-sensitive Geiger-mode avalanche photodiodes • 64 x 64 demonstration circuit (scalable) • Pixel size reduction from 100 mm to 30 mm • Timing resolution reduction from 1 ns to 0.1 ns • 100x reduction in voxel volume 3D-Integrated Tier-1/Tier-2 wafer pair electrical test vehicle 150 mm

Comparison CMOS vs. CCD for Astronomy Silicon PIN hybrid detectors have become a serious alternative to CCDs providing a number of significant advantages, specifically for large mosaic focal plane arrays.

CCD Transition CMOS Conclusion It’s happening!

CMOS Detector Technology