Xilinx FPGAs:Evolution and Revolution

1. Xilinx FPGAs:Evolution and Revolution

2. Evolution results in bigger, faster, cheaper FPGAs; better software with fewer bugs, faster compile times; coupled with better technical support.

3. Innovative architectural and circuit features with advancements in design methodology - modular team based design & internet based configuration method: resulting in Revolution.

4. A Decade of Progress

5. Xilinx FPGAs : An Endless Journey 1.5K 7.5K, 50MHz 85K, 80 MHz 16K, 50MHz 100MHz+ 40K 50K-1M, 200MHz 200K, 200MHz 4M, 250MHz 300K, 200MHz+ 40K-8M, 420MHz 10M, 420MHz

6. Xilinx FPGAs - Generic Features • High Performance at different voltages • Footprint Compatibility - Devices within each family are compatible. • Low power consumption/high performance • Integrated Software • Technology independence - EDIF, VHDL, Verilog, SDF interfaces.

7. XC2000 • First FPGA Family from Xilinx. • Two members: XC2064 1000 Gates XC2018 1500 Gates • Ext. Crystal Oscillator. • No Tri State Buffers. • XACT 1.0 Development System.

8. XC2000 • Max.Logic Gates 1500 • Max. CLB Flip-flop 100 • Max. I/O Pins 74 • Max. I/O Flip-Flop 74

9. XC3000 • Replaces TTL, MSI and other PLD logics. • Integrates complete subsystem into single Package. • System clock Speed up to 50 MHz. • On-chip crystal Oscillator. • Low-Skew Clock Nets. • Over 20 different Packaging Options • Interface to popular design Environment like Mentor, Cadence and View Logic.

10. XC3000 CLB

11. XC3100A • Ultra-high-speed Family with six members. • XC3195 in 22 X 22 CLB array size. • Compatible with XC3000. • Error checking of configuration bit stream.

12. XC4000 CLB

13. XC4000 Family Features • Synchronous Single and Dual-Port RAM • Internal Three-state buffers. • JTAG Boundary Scan • System performance to 80 MHz • 0.5 µ SRAM Process Technology

14. XC4000 Sub-Families Version Max. logic Max. I/O Voltage Gates XC4000XL 3k-85k 448 3.3 XC4000EX 28k, 36k 320 5 XC4000E 3.0-25k 256 5

15. XC5200 • Low Cost FPGA Family. • System Features: - Fast Arithmetic Functions - High Performance Clock Network - Highly routable - Easy Pin Locking - Fast wide Functions - Three-state buffers - JTAG - Performance up to 50 MHz.

16. Resource Comparison

17. Xilinx Spartan/XL FPGAs Xilinx 4000 Series Heritage Advanced Process Technology 100 MHz+ performance On-chip SelectRAM Software v4.2i Core solutions Small die size Low cost packaging Low test cost Total Cost Management

18. Total Cost Management • Leading edge process technology • Smallest die size of any FPGA with on-chip RAM • Focused package offering • Low-power architecture allows use of highest volume plastic packages • Streamlined test flow • Lower cost test hardware • Built-in self test features and shorter test times • Optimized manufacturing flows

19. Spartan-XL Family Advanced 0.35m Process • Transistor gates 0.35u • Allows 3.3 V supply • All other features 0.25u • Small size • Low capacitance • Performance Chip Combines 3.3 V operation with 0.25u benefits

20. Spartan Speed Grades • Higher speed grade = higher performance XL-5 XL-4 E-1 -4 E-2 Performance -3 -3 -4 XC5200 XC4000E Spartan Spartan-XL

21. What’s missing in Spartan? • No asynchronous RAM • Only RAM16(32)X1S, RAM16X1D, ROM16X1 • No edge decoders • No DECODEx • No wired-AND • No WANDx or WOR2AND • Mode pins not usable as I/O • No MD0, MD1, MD2

22. Virtex - features • Densities from 50 K to 1M system gates. • System performance up to 200 MHz. • Multi-standard Select IO interfaces. • Built-in clock-management circuitry - Four DLLs - Four Low-skew global Clock Distribution Net • Hierarchical Memory System. • Dedicated Multiplier Support.

23. Spartan-II - features • Densities as high as 200K gates. • Streamlined features based on Virtex architecture. • Very Low Cost • LUT Distributed RAM and Block RAM support. • Dedicated Multiplier support. • 4 DLLs

24. Virtex/Spartan-II CLB • 1 CLB holds 2 slices • Each slice has two sets of • Four-input LUT • Any 4-input logic function • Or 16-bit x 1 RAM • Or 16-bit shift register • Carry & Control • Fast arithmetic logic • Multiplier logic • Multiplexer logic • Storage element • Latch or flip-flop • Set and reset • True or inverted inputs • Sync. or Async. Control

25. Virtex/Spartan-II DLLs ImproveClock Networks Deskew Clocks on Board DLL1 DLL2 Deskew Clocks on Chip Cascade DLLs Manage Multiple System Clocks Convert Clock Levels using Select I/O DLL3 DLL4 Generate Clocks (Multiply, Divide, or Shift) Delay locked loops synchronize on-chip and board level clocks

26. Virtex-E – what’s added? • Up to 4 million system gates • 2-4X more Block RAM • 8 DLLs • Differential I/O signaling (LVDS/BLVDS) • some new speed grades.

27. Spartan-IIE - features • Density 50-300K • Supports LVDS • 4 DLLs • VCCINT – 1.8V • More speed grades than Spartan-II. • Less packaging Options.

28. Virtex-II • All Xilinx FPGAs contain the same basic resources • CLBs contain combinatorial logic and register resources • IOBs interface between the FPGA and the outside world • Programmable interconnect • Other resources • Three-state buffers • Global clock buffers • Boundary scan logic • Virtex-II devices contain additional resources • Block SelectRAM • Dedicated Multipliers • Digital Clock Manager (DCM)

29. TBUF TBUF CLB Tile COUT COUT Switch Matrix Slice S3 Slice S2 SHIFT Slice S1 Slice S0 Fast Connects CIN CIN

30. LUT LUT PRE D Q CE CLR Carry Carry PRE D Q CE CLR Slice Structure Slice 0

31. Mult-AND and dedicated Multiplier too • SRL16 • DDR Registers. • Fast Carry Logic • Digitally Controlled Impedance

32. CLB F8 F5 Slice S3 F6 Slice S2 F5 F7 Slice S1 F5 F6 Slice S0 F5 Connecting Function Generator

33. Select I/O • Allows direct connections to external signals of varied voltages and thresholds • Optimizes the speed/noise tradeoff • Saves having to place interface components onto your board • Differential signaling standards • LVDS, BLVDS, ULVDS • LDT

34. RAM16X1S D WE WCLK A0 O LUT LUT LUT A1 A2 A3 RAM32X1S RAM16X1D D D WE WE Slice WCLK WCLK A0 O A0 SPO A1 A1 A2 A2 A3 A3 A4 DPRA0 DPO DPRA1 DPRA2 DPRA3 Distributed and Block Select RAM

35. Dedicated Multiplier Block • Eighteen-bit 2’s complement signed operation • Optimized to implement Multiply / Accumulate functions • Multipliers are physically located next to block SelectRAM 18 x 18 Multiplier 4x4 signed ~255 MHz 8x8 signed ~210 MHz Output (36 bits) 12x12 signed ~170 MHz 18x18 signed ~140 MHz

36. DCM • Up to twelve DCMs per device • Located on top and bottom edges of the die • Driven by clock input pads • DCMs provide: • Delay-Locked Loop (DLL) • Digital Frequency Synthesizer (DFS) • Digital Phase Shifter (DPS) • Digital Spread Spectrum (DSS) • Up to four outputs of each DCM can drive onto global clock buffers • All DCM outputs can drive general routing

37. Challenges to accelerate Processing performance Very Large Single Task requires Parallel Processing TypesofChallenges Multiple Tasks Multiple Solutions Parallel Processing Using Multiple Processors Parallel Processing in Hardware Multiple Processors on Multiple Tasks • High performance • lower cost • low complexity • Specific task focus • Scalable

38. Virtex-II Pro Addresses All Processing Tasks Fabric for parallel processing in hardware Fabric for parallel processing in hardware Virtex-II Pro Fabric Virtex-II Pro Fabric • Uunmatched Performance • Uunmatched Flexibility Up to four 300MHz PowerPCs for multiple processing Up to four 300MHz PowerPCs for multiple processing

39. Logic Capacity and Features

40. Virtex II Pro Leads all the way

41. Supply Voltage • XC4000 and Spartan families use a 5V supply. • The-XL families use 3.3 V supply. • Virtex and Spartan-II use 2.5V supply. • Virtex-E uses 1.8 V. • Virtex-II and Virtex-IIPro uses 1.5 V

42. Xilinx Development System

43. THE FUTURE……. • In 2005, FPGAs will be built on 70nm-Cu process; will implement 50 million system gates; with 2 billion transistors on-chip; with 10 layers of copper metal; with embedded processors running at 1 GHz clock rate; with direct interface to 10 Gbps serial data.

44. URLs • www.xilinx.com • www.fpga-faq.com • www.optimagic.com • www.datasheetlocator.com • Newsgroup comp.arch.fpga

45. Thank You!!!!!!