1 / 25

Interconnect and Packaging

Interconnect and Packaging. Chung-Kuan Cheng UC San Diego. Lecture 8: Clock Meshes and Shunts. I. Clock Meshes. In Engineering practice, very deep balanced buffer tree + mesh is widely adopted for global clock distribution IBM Power 4: 64 by 64 grid at the bottom of an H-tree

yoshi
Download Presentation

Interconnect and Packaging

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Interconnect and Packaging Chung-Kuan Cheng UC San Diego Lecture 8: Clock Meshes and Shunts

  2. I. Clock Meshes • In Engineering practice, very deep balanced buffer tree + mesh is widely adopted for global clock distribution • IBM Power 4: 64 by 64 grid at the bottom of an H-tree • Intel IA: clock stripe at the bottom of a buffer tree. • “Skew Averaging”: shunt at different levels • “Skew Averaging Factor” determined by simulation. No guideline for routing resource planning known yet

  3. I. Clock Mesh Example (1) • DEC Alpha 21264

  4. I. Clock Mesh Example (2) • IBM Power4 • H-tree drives one domain clock mesh • 8x8 area buffers

  5. I. Clock Mesh Example (3) • Intel Pentium 4 • Tree drives three spines

  6. II. Multi-level mesh structure

  7. II. Linear Variations Model • Process variation model • Transistor length • Wire width • Linear variation model • Power variation model • Supply voltage varies randomly (10%)

  8. II. Simplified Circuit Model

  9. II. Transient Response when t<T VS1=u(t) Vs2=0 Let Then V1 = A + B V2 = A - B

  10. II. Transient Response when t>T Let: then

  11. II. Skew Expression • Assumptions: • T<<RsC • Rs /R <<RsC/T • Using first order • Taylor expansion ex=1+x,

  12. II. Spice Validation of Skew Function

  13. II. Skew on mesh • Conjectured skew expression • Using regression to get k

  14. II. K values for n by n meshes

  15. II. Optimization • Skew function • Multi level skew function

  16. III. Experimental Settings GND + - GND • Die size 1cm by 1cm • 100nm copper technology • Ground Shielded Differential Signal Wires for Global Clock Distribution • Routing area is normalized to the area of a 16 by 16 mesh with minimal wire width

  17. III. Experimental Results • Optimized wire width

  18. III. Optimal Routing Resources Allocation total area level-4 level-3 level-2 level-1

  19. III. Skew reduction V.S. Mesh Area

  20. III. Experiments—Optimized Skew

  21. III. Delay Surfaces

  22. III. Robustness Against Supply Voltage Variations

  23. III. Inductance Considerations • Delay error between RC and RLC will not exceed 15 % under following conditions: • CL >> C • R/Z0 > 2 • R1 > nZ0(n is between 0.5 and 1.0) (In our network, working at 4G, Z0=339ohm R1=367ohm, R=5130ohm, Cl=149.4fF, and C=14.3fF)

  24. IV. Simulation Results with inductance Spice simulation results at 4GHz Without L With L

  25. IV. Inductance Diminishes Shunt Effects • 0.5um wide 1.2 cm long copper wire • Input skew 20ps

More Related