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FPGA Design Flow

FPGA Design Flow. Course Agenda. Day One Objectives. Describe general FPGA architectures and the Xilinx design flow Use the architecture wizard to generate a DCM Use the Xilinx Constraints Editor to enter global timing constraints

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FPGA Design Flow

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  1. FPGA Design Flow Course Agenda This material exempt per Department of Commerce license exception TSU

  2. Day One Objectives • Describe general FPGA architectures and the Xilinx design flow • Use the architecture wizard to generate a DCM • Use the Xilinx Constraints Editor to enter global timing constraints • Run behavioral simulation on an FPGA design that contains IP cores generated from Core Generator • Understand the basics of the PicoBlaze 8-bit controller After completing this course, you will be able to:

  3. Day Two Objectives • Pinpoint design bottlenecks by using the Timing Analyzer reports • Describe different synthesis options and how they can improve performance • Understand the various implementation options • Create and integrate cores into your design flow by using the CORE Generator™ system • Use Chipscope-Pro to perform an on-chip verification After completing this course, you will be able to:

  4. Prerequisites • Basic HDL knowledge (VHDL or Verilog) • Digital design knowledge and experience • Understanding of PicoBlaze

  5. Day 1 Agenda • Basic FPGA Architecture • Xilinx Tool Flow • Lab 1: Xilinx Tool Flow Demo • Architecture Wizard and PACE • Lab 2: Architecture Wizard and PACE • Reading Reports • Global Timing Constraints • Lab 3: Global Timing Constraints • FPGA Design Techniques

  6. Day 2 Agenda • Synchronous Design Techniques • Floorplanner • Synthesis Techniques • Lab 4: Synthesis Techniques • Implementation Options • CORE Generator™ System • Lab 5: CORE Generator System • Chipscope-Pro • Lab 6: Chipscope-Pro

  7. Appendix Presentations • Designing with the Digital Clock Manager (DCM) • Power Estimation

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