"Implementation Trade-offs of Triple-DES in the SRC Reconfigurable Computing Environment"

1. "Implementation Trade-offs of Triple-DES in the SRC Reconfigurable Computing Environment" Osman Devrim Fidanci 1, Hatim Diab 1, Tarek El-Ghazawi 1, Kris Gaj 2 and Nikitas Alexandridis 1 1: George Washington University 2: George Mason University

2. Outline • Why Reconfigurable Computing • SRC Reconfigurable Super Computer • Hardware Architecture • Compiler Architecture • Macro Development for SRC • Triple DES Encryption Algorithm • Single DES Algorithm • Triple DES with 2 Keys • Implementation Trades of Triple-DES in SRC • Conclusions D3

3. Why Reconfigurable Computing ? Performance • Direct instantiation of hardware resulting in better efficiency • Reduces I/O bandwidth requirements by elimination of Load/Store paradigm Scalability • Basic technology improving much faster than Moore’s law • Takes advantage of parallelism found in many programs Time to Solution • Can be programmed like a microprocessor • Uses standard operating system and tools D3

4. Xeon mP Xeon mP L2 L2 L2 L2 Control Chip Control Chip MIOC MIOC SNAP SNAP On-Board Memory (24 MB) On-Board Memory (24 MB) PCI Slot PCI Slot User Chip User Chip User Chip User Chip SRC-6E Hardware Architecture mP Board mP Board Xeon mP Xeon mP MAP Board (6x) (6x) Private Memory Private Memory (6x) (6x) D3

5. SRC MAP Compiler Architecture RC Compiling System Application Executable Optimization HLL Source FORTRAN & C DFG Generation Logic Partitioning Verilog Generation Synthesis Place & Route MAP Macros Customer Macros Run-time Library D3

6. Advantages of SRC Hardware • Introduction of the SNAP card • Data feed to the FPGA though Memory bus with 800 MB/s peak (theoretical) • Eliminating the PCI bottleneck in traditional FPGA cards D3

7. SRC-6E System SW • System • Linux • Red Hat 7.2 • Driver and Library additions to support SNAP and MAP • Compilers • Microprocessor and MAP • Tools • WINE • FPGA • Synplicity Synplify Pro • Xilinx Integrated Software Environment D3

8. Macro Development for SRC • User macro can be defined in Verilog or VHDL • Three types of macro defined in SRC platform: • Functional • Stateful • External • System clock frequency is 100MHz. So, User macros must be optimized for this speed. Otherwise FIFO must be employed D3

9. General Depiction of DES Encryption Algorithm • 64-bit inputs (plaintext and keys) • 64-bit output (ciphertext) • 16-round operation plus initial permutations • Pipelined, 17-clock cycles latency • Output generated at every clock cycle D3

10. Single Round of DES Algorithm • Expansion/permutation operation (E-table) • Logical XOR operations • Substitution/choice operation (S-box) • Permutation (P) D3

11. Triple DES with 2 Keys Encipher • “Triple-DES with two keys” scheme is used for backward compatibility with DES (by setting two keys identical, provides single DES encryption/decryption). • Triple DES requires 51-clock cycle to get ciphertext Decipher D3

12. Different Implementations of Triple DES in SRC • Calling DES macro three times from Fortran main file (1) • Calling DES macro three times from Fortran subroutine file (2) • Calling Triple-DES macro once from Fortran main and subroutine files (3) D3

13. Calling DES/Tri-DES macro from Fortran HLL Main.f90 1 time 3 times 1 time Subroutine1.mf Subroutine2.mf Subroutine3.mf 1 time 3 times 1 time DES.v DES.v Tri-DES.v (1) (2) (3) D3

14. Implementation Trade Offs of Triple DES in SRC D3

15. Lessons Learned • Case1 provides the smallest gate count, the highest speed but the longest processing time. • Case2 provides the highest gate count, the lowest speed but the shortest processing time. • Case3 provides the slightly smaller gate count than Case2, the slightly slower speed than Case1 but the shortest processing time. D3