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Scribe(27-03-2014) Rhitottam De 11CS30011

Scribe(27-03-2014) Rhitottam De 11CS30011. Implementation of Page Table. For each process the page table may be stored as follows :-

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Scribe(27-03-2014) Rhitottam De 11CS30011

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  1. Scribe(27-03-2014) Rhitottam De 11CS30011

  2. Implementation of Page Table • For each process the page table may be stored as follows :- a) In a set of registers (special purpose) : During context switch the contents of these registers is stored in the PCB besides that of other registers. If the number of entries in the page table is very large then many new registers will be needed. b) Main memory : Two special purpose registers – Page table base register and Page table length register can be used to access the page table of each process. But here each read/write instruction would require two memory access-one for page table and one for data/instruction. c)Maintain a special fast-lookup hardware cache called ‘associative memory’ or ‘transition look-aside buffers’ for storing the page table entries

  3. Implementation of Page Table Address translation(p,d) : If p is in associative memory get the frame number out. Otherwise search the frame from page table in the memory.

  4. Implementation of Page Table • During context switch the contents of the TLB is flushed out and it is filled again for another process. In between context switch the TLB is completely cleaned out and gradually refilled. • Advanced Techniques :- • - Do not flush the TLB for kernel processes . Flush the TLB for user processes. • - Some TLBs store ASIDs (Address Space Identifiers) which is the process id to uniquely identify entries for process to provide address-space protection for that process.

  5. Implementation of Page Table • This ensures that the TLB need not be flushed out each time . But here, we need to additionally match the process id to ensure that the entry corresponds to that process only . If match is found then HIT is declared.Otherwise MISS is declared.

  6. Implementation of Page Table • Effective Access Time : • Associative Lookup =  time unit • Can be < 10% of memory access time • Hit ratio =  • Hit ratio – percentage of times that a page number is found in the associative registers; ratio related to size of TLB • Consider  = 80%,  = 20ns for TLB search, 100ns for memory access • Effective Access Time (EAT) = (100 + )  + (200 + )(1 – ) • Consider  = 80%,  = 20ns for TLB search, 100ns for memory access • EAT = 0.80 x 120 + 0.20 x 220 = 140ns • Consider slower memory but better hit ratio ->  = 98%,  = 20ns for TLB search, 100ns for memory access • EAT = 0.98 x 120 + 0.02 x 220 = 122ns

  7. Implementation of Page Table • Memory Protection : • - Memory protection is implemented by associative protection bit with each frame to indicate only if read-only or read-write access is allowed. • - Valid-Invalid bit attached to each entry in the page table • a) Valid - the page is in the process’s logical address space. • b) Invalid – page is not the process’s logical address space.

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