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Verification Technologies IBM Haifa Labs

Formal Specification Using Sugar 2.0. Cindy Eisner. September 2002. Verification Technologies IBM Haifa Labs. Overview. Declarative language for specification of hardware Concise, intuitive formalism to reason about behavior over time Combines temporal logic and regular expressions

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Verification Technologies IBM Haifa Labs

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  1. Formal Specification Using Sugar 2.0 Cindy Eisner September 2002 Verification Technologies IBM Haifa Labs

  2. Overview • Declarative language for specification of hardware • Concise, intuitive formalism to reason about behavior over time • Combines • temporal logic and • regular expressions • under a convenient layer of user-friendly syntactic sugar • Sugar is used as: • easy-to-read but precise specification • input to formal verification • source of automatically generated checkers for simulation

  3. History • 1994 • Syntactic sugaring of CTL for RuleBase model checker • 1995 • Addition of regular expressions • 1997 • Automatic generation of simulation monitors ________________________________________________ ________________________________________________ • 2001 • Move to linear (LTL-based) semantics • 2002 • Selected by Accellera for IEEE standardization Sugar 1.0 Sugar 2.0

  4. Track Record (Sugar 1.0) • IBM products: • Main Frame line (S/390) • Midrange line (AS/400) • Workstation line (RS/6000) • PC line (Netfinity) • Super Computers (ASCI) • ASIC/OEM business • External licensees • University program

  5. Sugar 2.0 - The Language Modeling Verification Temporal Boolean

  6. The Temporal Layer Modeling Verification Temporal Boolean

  7. Simple Invariants • If data_en is de-asserted, then data_out must be de-asserted as well. • always (!data_en -> !data_out) • Signals ena and enb are never asserted simultaneously. • never (ena & enb)

  8. Relations Over Time • If req is asserted, then ack must be asserted the following cycle. • always (req -> next ack) • If req is asserted, ack must be asserted four cycles later. • always (req -> next[4] ack) • If req is asserted, ack must be asserted some time in the future. • always (req -> eventually! ack)

  9. Relations Over Time, cont. • Whenever a high priority request is received, the next grant should be to a high priority requester. • always (hi_pri_req -> next_event(grant)(dst=hi_pri)) • Whenever a request is issued, signal last_ready must be asserted on the fourth assertion of signal ready. • always (req -> next_event(ready)[4](last_ready))

  10. Regular Expressions • If req is asserted, then eventually we must see an ack that is not aborted. • always (req -> eventually! {ack ; !abortin}) req ack abortin

  11. Regular Expressions, cont. • A sequence of req followed by ack should be followed by a full data transaction: an assertion of start_trans, followed by eight consecutive data transfers, followed by the assertion of end_trans. • always {req;ack} |=> {start_trans;data[*8];end_trans} req ack starttrans data endtrans

  12. Regular Expressions, cont. • A sequence of req followed by ack should be followed by a full data transaction: an assertion of start_trans, followed by eight (not necessarily consecutive) data transfers, followed by the assertion of end_trans. • always {req;ack} |=> {start_trans;data[=8];end_trans} req ack starttrans data endtrans

  13. Hardware clocks • Consider only cycles in which the clock ticks • always (req -> next[4] ack) @ (clk) clk req ack

  14. Hardware clocks, cont. • Support for multiply-clocked designs • always (p -> next (q@clkq))@clkp i p clkp q clkq

  15. Hardware resets • Synchronous reset • always • ({req;ack} |-> {start;data[*8];end} abort reset) @ (clk) • Asynchronous reset • always • (({req;ack} |-> {start;data[*8];end}) @ (clk)) abort reset)

  16. Standardization: Status • Endorsed publicly by many EDA vendors, including: • Cadence • Mentor Graphics • Co-Design Automation • 0-In Design Automation • Novas Software • Accellera recommendation will be submitted to IEEE by year end 2002 • Real Intent • TransEDA • Verplex • Veritable • Structured Design Verification

  17. Tool Support Company Tool Function IBM Model Checker RuleBase IBM Generator of Simulation Monitors FoCs NoBug Consulting Specification Compiler S2E TransEDA Dynamic Property Checker VN-Property DX Cadence Dynamic + Static Property Checking Verification Cockpit Avery Testbench Automation Tool TestWizard TNI/Valiosys Model Checker imPROVE-HDL Esterel Full-flow solution for design & verification Esterel Suite @HDL Model Checker @Verifier 0-In CheckerWare Library of Protocol Checkers

  18. Sugar home page • More information available on the Sugar home page at: • www.haifa.il.ibm.com/projects/verification/sugar/index.html • Complete definition • Tutorial • Sugar parser • more

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