Redesign of a Microprocessor with no Impact to the Mission Software

1. Redesign of a Microprocessor with no Impact to the Mission Software Keith Bergevin Senior Design Engineer Defense Microelectronics Activity

2. Microprocessor ObsolescencePresents Difficult Options Option 1: Replace with state-of-the-art COTS processor • Large costs incurred to modify and certify the software Option 2:Redesign at the sub-system or system level • Frequent Redesigns viable for cell phones, but NOT Military Systems with a 25 year life expectancy Option 3: Legacy software emulation on COTS processor • Large investment in tool suite Option 4: FPGA emulation of existing processor? Bergevin D3

3. Successful FPGA Redesignof a Custom Microprocessor • Problem: Obsolete Missile Bourne Computer Microprocessor in Evolved Sea Sparrow Missile (ESSM) • Custom Raytheon design • 1.2 micron CMOS • Variable clock frequency • > $25M if modification to S/W required • DMEA Solution: Xilinx Virtex XCV300 implementation • 100% software compatible • How was it done? Bergevin D3

4. Briefing Roadmap • Original documentation: Don’t think it’s accurate! • Characterization of legacy component: The real key. • FPGA Simulation: The heart of the redesign effort. • Stand-alone FPGA test: Verification of the hardware. • Module implementation: Overcome the final issues. Bergevin D3

5. Original Documentation: Not Always Accurate! • Vendor data sheets • Good starting point • Often not accurate • Specific Examples: • Z8001 “POP” Instruction: POP address, @Rs • Data Book: States 18 cycles for Direct Address mode • DMEA measured 19 cycles • ESSM microprocessor schematic diagram: • Buffers displayed as inverters Bergevin D3

6. Device Characterization: Road to an Accurate Specification • Extract device data directly from the original microprocessor • Test vectors driven into device for all functions • Start-up • Instruction Set - Including all addressing modes • Interrupts • Internal micro-code • Accuracy assured by measuring actual device Bergevin D3

7. Characterization Process Design Custom Device Adapter: Interface To Chip Tester Instrument Measurement System Apply Test Vectors to Inputs Extract & Save Outputs in Spreadsheet Excel Spreadsheet Format Vectors to Target FPGA Simulators Xilinx, Mentor, Synopsys Bergevin D3

8. Key Characterization Example:Extracting the Micro-code • ESSM micro-code controls all major functions • 704 by 64 bit instructions stored in internal ROM • 256 basic assembly instructions • DMEA devised method to extract the entire ROM • Halt processor • Load micro-code 64 bit register with next instruction • Halt processor • Shift micro-code for 64 clock cycles • Repeat steps 1-4 for locations 1 through 704 Bergevin D3

9. DMEA Custom Device Adapterwith Legacy Microprocessor Bergevin D3

10. FPGA Design & Simulation • Design • Functions entered in Schematic Capture and VHDL • Capture for standard functions: registers, counters, etc. • VHDL for all other functions: memory arrays, multipliers, etc. • Primary Design Tool: Xilinx ISE • Simulation • Two sets of test vectors applied: • Vectors developed by design engineer • Vectors extracted from device characterization • Primary simulation tools: Mentor ModelSim, Synopsys Bergevin D3

11. Key Simulation Example • ESSM Microprocessor fails FMY instruction for commutative property • Design simulation of original schematic had different values when swapping operands • Circuitry was modified in VHDL to “correct” the function • Characterization vectors then “failed” the “corrected” instruction • DMEA determined the original hardware was implemented incorrectly • Confirmed with Raytheon software engineers • “Incorrect” circuitry implemented in the redesign to ensure the part functions as the original!! Bergevin D3

12. FPGA Selection • Key requirements • Sufficient density & clock speed • I/O 5V TTL compatible • Industrial grade temperature • Selection: Xilinx XCV300-5PQ240I FPGA • 2.5V Internal, 3.3V I/O, compatible with 5V TTL • 24.576 MHz system clock applied • 36K gates utilized • 91% of slices utilized Bergevin D3

13. DMEA Custom Device Adapterwith Xilinx FPGA Bergevin D3

14. FPGA Hardware Testing • Test 1: Stand-alone test • Replace ESSM custom microprocessor with Xilinx FPGA on DMEA test adapter board • Comprehensive testing of start-up, Interrupts, Instruction Set, etc. • Over 10 Million vectors, 144 bits per vector applied to test • Test 2: Module and system level testing • Xilinx XCV300 designed into ESSM microprocessor module • Passes 100% of Raytheon system level testing Bergevin D3

15. Top: Legacy Module with ProcessorBottom: Redesigned with FPGA Bergevin D3

16. Lessons Learned & Summary • A Comprehensive characterization of the obsolete custom microprocessor was the critical element • Required exercising the complete instruction set • Extracting the internal micro-code was essential • Absolutely THE reason that any of the errors were found! • Replacing an obsolete microprocessor with an FPGA is a viable solution • 3.5 Engineers over 1 year vs. $25M+ to modify the software Bergevin D3